IP Library Granted Patent US 7,119,720
Granted Patent B2
US 7,119,720 · App. 11/145,714 · Granted Oct 10, 2006

Precision pulse placement to form a binary pulse signal

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Quick Facts
Patent No.
US 7,119,720
App. No.
11/145,714
Granted
Oct 10, 2006
Kind
B2
Abstract

The present invention relates to a method for pulse placement to form a binary pulse signal, said binary pulse signal having a constant pulse rate being reciprocal of a constant pulse rate period, comprising the steps of generating a bit clock having a bit clock period of shorter duration than said constant pulse rate period, synthesizing pulses with leading and trailing edges, said leading and trailing edges of said synthesized pulses being placed at N-multiples of said bit clock period within said constant pulse rate period, with N=0, 1, 2, . . , and selecting said bit clock period individually for successive pulses of said binary pulse signal.

Claims (21)

1. A method for pulse placement to form a binary pulse signal of subsequent binary pulses having individual pulse widths, at a constant pulse rate being a reciprocal of a constant pulse rate period, said method comprising:

generating a bit clock having a bit clock period of shorter duration than said constant pulse rate period,

synthesizing pulses with leading and trailing edges, said leading and trailing edges of said synthesized pulses being placed at N-multiples of said bit clock period within said constant pulse rate period, with N being any natural number including zero, and

selecting said bit clock period individually for successive pulses of said binary pulse signal as a function of the corresponding pulse widths.

2. The method of claim 1 , wherein selecting the bit clock period is performed by determining for each pulse an ideal pulse width, determining for a plurality of different bit clock periods corresponding quantization errors indicating each the difference between the ideal pulse width and the N-multiple of the bit clock period, and choosing out of the plurality bit clock periods the bit clock period with a minimum quantization error.

3. The method of claim 1 , characterized in that said method uses at least two sources supplying said bit clock period, wherein only one bit clock source is used for synthesizing a pulse at a time, while at least one of the further sources is prepared to supply said bit clock period for a subsequent pulse.

4. The method of claim 1 , characterized in that said pulse placement represents a pulse width modulation, including leading PWM, trailing PWM and dual sided PWM.

5. The method of claim 1 , characterized in that said placement of said leading and trailing edges of said pulses to be synthesized is determined by an algorithm, in particular a pulse width defined by said leading and trailing edges of said pulses to be synthesized is determined by an algorithm, said algorithm preferably includes natural sampling, uniform sampling, zero position coding or click modulation.

6. The method of claim 5 , characterized in that said method further comprises noise-shaping of a quantization error, said quantization error is caused by the deviation of realizable pulse widths from ideal pulse widths, wherein said ideal pulse widths are determined by said algorithm.

7. The method of claim 1 , characterized in that said method is used for pulse-based signal generation of a predetermined analog signal using a waveform generator.

8. The method of claim 7 , characterized in that control data for said waveform generator is either pre-processed and stored in a memory, or provided by a real-time algorithm, or a combination of both, wherein said control data is based on a signal processing which selects said bit clock period for minimum absolute quantization error.

9. The method of claim 1 , characterized in that said constant pulse rate period is based on a N/M Phase Locked Loop.

10. A computer readable storage media comprising executable computer program instructions that when executed cause a processing system to perform a method for pulse placement to form a binary pulse signal of subsequent binary pulses having individual pulse widths, at a constant pulse rate being a reciprocal of a constant pulse rate period, wherein said method includes:

comprising instructions for controlling a processor to execute a method for pulse placement to form a binary pulse signal of subsequent binary pulses signal having individual pulse widths, at a constant pulse rate being reciprocal of a constant pulse rate period, wherein said method includes:

generating a bit clock having a bit clock period of shorter duration than said constant pulse rate period,

synthesizing pulses with leading and trailing edges, said leading and trailing edges of said synthesized pulses being placed at N-multiples of said bit clock period within said constant pulse rate period, with N being any natural number including zero, and

selecting said bit clock period individually for successive pulses of said binary pulse signal as a function of the corresponding pulse widths.

11. A system for pulse placement to form a binary pulse signal, said binary pulse signal having individual pulse widths, at a constant pulse rate being a reciprocal of a constant pulse rate period, said system comprising:

a generator that generates a bit clock having a bit clock period of shorter duration than said constant pulse rate period,

a synthesizer that synthesizes pulses with leading and trailing edges, said leading and trailing edges of said synthesized pulses being placed at N-multiples of said bit clock period within said constant pulse rate period, with N being any natural number including zero, and

a selector that selects said bit clock period individually for successive pulses of said binary pulse signal as a function of the corresponding pulse widths.

Assignments (6)
CHANGE OF ADDRESS Recorded Dec 18, 2018
From: ADVANTEST CORPORATION
To: ADVANTEST CORPORATION
Reel/Frame 047987/0626 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 035371 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 14, 2015
From: ADVANTEST (SINGAPORE) PTE. LTD.
To: ADVANTEST CORPORATION
Reel/Frame 035425/0768 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2015
From: ADVANTEST (SINGAPORE) PTE. LTD.
To: ADVANTEST CORPORATION
Reel/Frame 035371/0265 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2012
From: VERIGY (SINGAPORE) PTE LTD
To: ADVANTEST (SINGAPORE) PTE LTD
Reel/Frame 027896/0018 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 14, 2007
From: AGILENT TECHNOLOGIES, INC.
To: VERIGY (SINGAPORE) PTE. LTD.
Reel/Frame 019015/0119 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 6, 2005
From: RIVOIR, JOCHEN
To: AGILENT TECHNOLOGIES, INC.
Reel/Frame 016675/0001 →