System and method for electronic testing of multiple memory devices
View Patent ↗A testing device may include a memory controller managing a transfer of data; and a plurality of interface boards. Each interface board includes a controller buffer. Each controller buffer transfers data between the memory controller and at least one memory module. The memory controller tests the at least one memory module. The testing device is operable to test the at least one memory module independent of an operating rate of the at least one memory module. The memory controller receives operating data of the at least one memory module.
1. A testing device, comprising:
a memory controller managing a transfer of data; and
a plurality of interface boards, each interface board including a controller buffer, each controller buffer transferring data between the memory controller and at least one memory module, each controller buffer is connected to the memory controller independently of the other controller buffers,
wherein the memory controller tests the at least one memory module, the testing device operable to test the at least one memory module independent of an operating rate of the at least one memory module, the memory controller receiving operating data of the at least one memory module, each memory module is connected to only one of the controller buffers.
2. The testing device of claim 1 , wherein the controller buffer is an advanced memory buffer.
3. The testing device of claim 1 , wherein the at least one memory module includes a plurality of memory modules.
4. The testing device of claim 3 , wherein the plurality of memory modules exhibits one of a daisy architecture and a serially linear architecture.
5. The testing device of claim 1 , being configured to test the at least one memory module including a plurality of dynamic access memories.
6. The testing device of claim 1 , being configured to test the at least one at least one memory module including a memory buffer.
7. The testing device of claim 6 , wherein the memory buffer is an advanced memory buffer.
8. The testing device of claim 6 , wherein the at least one memory module is a fully-buffered dual in-line memory module.
9. The testing device of claim 6 , wherein the memory controller writes to the at least one memory module through the controller buffer and the memory buffer.
10. The testing device of claim 1 , further comprising:
a repeater disposed between the memory controller and the at least one memory module to amplify signals carrying the data.
11. A method, comprising:
generating, by a memory controller, a set of test data;
transferring, by the memory controller, the set of data to a plurality of interface boards, each interface board including a controller buffer, each controller buffer is connected to the memory controller independently of the other controller buffers;
transferring, by the controller buffers, the set of data to at least one memory module connected to each interface board, wherein the controller buffer operates independent of an operating rate of the at least one memory module, each memory module is connected to only one of the controller buffers; and
receiving operating data of the at least one memory module in response to the set of test data.
12. The method of claim 11 , wherein the controller buffer is an advanced memory buffer.
13. The method of claim 11 , wherein the at least one memory module includes a plurality of memory modules.
14. The method of claim 13 , wherein the plurality of memory modules exhibits one of a daisy architecture and a serially linear architecture.
15. The method of claim 11 , wherein the at least one memory module includes a plurality of dynamic access memories.
16. The method of claim 11 , wherein the at least one memory module includes a memory buffer.
17. The method of claim 16 , wherein the memory buffer is an advanced memory buffer.
18. The method of claim 16 , wherein the at least one memory module is a fully-buffered dual in-line memory module.
19. The method of claim 11 , further comprising: amplifying signals corresponding to the transfer of data through a repeater disposed between the memory controller and the at least one memory module.
20. A testing device, comprising:
a memory controller managing a transfer of data; and
a plurality of connection means, each connection mean including a buffering means, each buffering means transferring data between the memory controller and at least one memory module, each buffering means is connected to the memory controller independently of the other buffering means,
wherein the memory controller tests the at least one memory module, the testing device operable to test the at least one memory module independent of an operating rate of the at least one memory module, the memory controller receiving operating data of the at least one memory module, each memory module is connected to only one of the buffering means.