IP Library Granted Patent US 7,123,508
Granted Patent B1
US 7,123,508 · App. 10/919,956 · Granted Oct 17, 2006

Reference cells for TCCT based memory cells

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Quick Facts
Patent No.
US 7,123,508
App. No.
10/919,956
Granted
Oct 17, 2006
Kind
B1
Abstract

A reference cell produces a reference current that is about half of the current produced by a memory cell. The reference cell is essentially the same as the memory cell with an additional current reduction device that can be a transistor. Adjusting a reference voltage applied to the transistor allows the reference current to be varied. A control circuit to produce the reference voltage includes dedicated memory and reference cells and a feedback circuit that compares the two cells' currents. The feedback circuit applies the reference voltage to the reference cell of the control circuit and adjusts the reference voltage until the current from the reference cell is about half of the current from the memory cell. The reference voltage is then applied to other reference cells in a memory array.

Claims (12)

1. A memory array comprising:

a memory cell having a first voltage applied thereto and including a logical state and configured to generate a first current on a first bit line;

a reference voltage generator circuit having the first voltage applied thereto and configured to generate a reference voltage;

a reference cell configured to receive the reference voltage and to generate a second current on a second bit line;

means for determining the logical state of the memory cell by comparing the first current to the second current; and

first and second word lines;

wherein the memory cell is a TCCT based memory cell including an NDR device disposed adjacent to the second word line, and a pass transistor with a gate coupled to the first word line.

2. The memory array of claim 1 wherein the reference cell is a TCCT

based cell including

an NDR device disposed adjacent to the second word line, and

a first pass transistor with a gate coupled to the first word line.

3. The memory array of claim 1 wherein the means for determining the logical state of the TCCT based memory cell is a sense amplifier.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2013
From: T-RAM SEMICONDUCTOR, INC.
To: T-RAM (ASSIGNMENT FOR THE BENEFIT OF CREDITORS), LLC
Reel/Frame 031694/0018 →
PURCHASE OPTION AGREEMENT Recorded Jun 3, 2010
From: T-RAM SEMICONDUCTOR, INC.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 024474/0979 →
RELEASE Recorded May 18, 2010
From: SILICON VALLEY BANK
To: T RAM SEMICONDUCTOR INCORPORATED
Reel/Frame 024492/0651 →
SECURITY AGREEMENT Recorded Aug 7, 2008
From: T-RAM SEMICONDUCTOR INCORPORATED
To: SILICON VALLEY BANK
Reel/Frame 021354/0186 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 17, 2004
From: HORCH, ANDREW; SAMADDAR, TAPAN
To: T-RAM, INC.
Reel/Frame 015750/0518 →