Standard cell back bias architecture
View Patent ↗An apparatus including, in one embodiment, a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential. Such an embodiment also includes a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potential.
1. An apparatus, comprising:
a CMOS device cell including at least first and second CMOS transistors having first and second CMOS transistor doped regions in first and second doped wells, respectively, wherein the first and second doped wells have opposite dopant types, and wherein each of the first and second CMOS transistor doped regions is configured to be biased with a corresponding one of a power supply potential and a ground potential; and
a tap cell having first and second tap cell doped regions in the first and second doped wells, respectively, wherein each of the first and second tap cell doped regions is configured to be biased with a different potential relative to the power supply and ground potentials, wherein the first tap cell doped region has the same dopant type as the first doped well but a higher dopant concentration relative to the first doped well, and wherein the second tap cell doped region has the same dopant type as the second doped well but a higher dopant concentration relative to the second doped well.
2. The apparatus of claim 1 wherein the first and second tap cell doped regions are configured to be biased with different first and second potentials, respectively, that are each a different potential relative to the power supply and ground potentials.
3. The apparatus of claim 1 wherein the CMOS device cell is a standard library cell.
4. The apparatus of claim 3 wherein the tap cell and the CMOS device cell have substantially similar shapes and lateral dimensions.
5. The apparatus of claim 1 wherein at least one of magnitude and amplitude of the different potential is different relative to the power supply and ground potentials.
6. The apparatus of claim 1 wherein at least one of phase and polarity of the different potential is different relative to the power supply and ground potentials.
7. The apparatus of claim 1 wherein the first and second tap cell doped regions are configured to be biased at times in addition to when the power supply potential is biasing the corresponding one of the first and second CMOS transistor doped regions.
8. An apparatus, comprising:
an N well located in a substrate;
a P well located in the substrate proximate the N well;
a tap cell including an N+ doped region in the N well and a P+ doped region in the P well;
a plurality of CMOS device cells each including a plurality of CMOS transistor devices each having source/drain regions in a corresponding one of the N well and the P well;
power supply and ground interconnects configured to connect the source/drain regions of ones of the plurality of CMOS transistor devices at least indirectly to a corresponding one of a power supply and ground to bias the connected source/drain regions with a corresponding one of a power supply potential and a ground potential; and
a first back-bias interconnect and a second back-bias interconnect configured to connect the N well and the P well, respectively, at least indirectly to first and second back-bias sources to bias the N well and the P well with a first and second back-bias potential, respectively, that are each a different potential relative to the power supply and ground potential.
9. The apparatus of claim 8 further comprising an interconnect structure including first and second metal layers having a plurality of conductive members interconnecting ones of the plurality of CMOS transistor devices to form ones of a plurality of CMOS device cells included in the apparatus, wherein the power supply and ground interconnects each at least partially include one of the plurality of conductive members in the first metal layer, and wherein the first and second back-bias interconnects each at least partially include one of the plurality of conductive members in the second metal layer.
10. The apparatus of claim 8 wherein the power supply and ground interconnects are substantially parallel, and wherein the first and second back-bias interconnects are substantially parallel and each substantially perpendicular to the power supply and ground interconnects.
11. The apparatus of claim 8 wherein:
the N well is one of a plurality of N wells each located in the substrate;
the P well is one of a plurality of P wells each located in the substrate;
the tap cell is one of a plurality of tap cells each including an N+ doped region in a corresponding one of the plurality of N wells and a P+ doped region in a corresponding one of the plurality of P wells; and
a plurality of CMOS device cells included in the apparatus collectively compose a plurality of cell blocks each associated with at least one of the plurality of tap cells.
12. The apparatus of claim 11 wherein each of the plurality of tap cells is oriented proximate a perimeter of a corresponding one of the plurality of cell blocks.
13. The apparatus of claim 11 wherein each of the plurality of tap cells is oriented in a central portion of a corresponding one of the plurality of cell blocks.
14. The apparatus of claim 8 wherein the N well and the P well are electrically isolated from the substrate.
15. The apparatus of claim 14 wherein a deep doped well electrically isolates the N well and the P well from the substrate.
16. The apparatus of claim 8 further comprising an isolation structure interposing the N well and the P well in the substrate.