Envelope detector with DC level shifting
View Patent ↗An envelope detector that does not generate an undesirable DC offset at its DC output signal. An envelope detector according to the present teachings includes a circuit for performing a DC level shift on an AC input signal applied to the envelope detector such that a magnitude of the DC level shift is proportional to a peak envelope of the AC input signal.
1. An envelope detector comprising a circuit for performing a DC level shift on an AC input signal applied to the envelope detector such that a magnitude of the DC level shift is proportional to a peak envelope of the AC input signal;
wherein the circuit for performing a DC level shift comprises a series capacitor and a shunt diode;
wherein the circuit further comprises:
a first node for receiving the AC input signal;
a second node, wherein the series capacitor is coupled between the first and the second nodes;
a bias current source, wherein the shunt diode is coupled between the bias current source and the second node;
a third node between the bias current source and the shunt diode; and
a second diode coupled between the third node and ground.
2. The envelope detector of claim 1 , wherein the series capacitor is selected to sample relatively a small amount of the AC input signal.
3. The envelope detector of claim 1 , further comprising a low pass filter coupled to the circuit.
4. The envelope detector of claim 1 , wherein the bias current source applies a bias current to the shunt diode and a bias current to the second diode.
5. An envelope detector comprising a circuit for performing a DC level shift on an AC input signal applied to the envelope detector such that a magnitude of the DC level shift is proportional to a peak envelope of the AC input signal, the envelop detector comprising:
a DC level shifting circuit comprises a series capacitor and a shunt diode;
a second diode, wherein the second diode is selected to be larger than the shunt diode; and
a bias circuit for applying a bias current to the shunt diode and a bias current to the second diode.
6. The envelope detector of claim 1 , wherein the second diode and the shunt diode are diode-wired transistors.
7. A method for envelope detection comprising performing a DC level shift on an AC input signal such that a magnitude of the DC level shift is proportional to a peak envelope of the AC input signal;
wherein said performing a DC level shift comprises charging a series capacitor and a shunt diode that receive the AC input signal;
wherein said performing a DC level shift comprises:
coupling the AC input signal to a first node;
coupling the series capacitor between the first node and a second node; and
coupling the shunt diode between a bias current source and the second node;
coupling a second diode between a third node and ground, wherein the third node is located between the bias current source and the shunt diode; and
providing the second diode and the shunt diode by diode-wiring a pair of transistors.
8. The method of claim 7 , further comprising selecting the series capacitor to sample relatively a small amount of the AC input signal.
9. The method of claim 7 , further comprising low pass filtering an output signal from the circuit.
10. The method of claim 7 , wherein the bias current source applies a bias current to the shunt diode and a bias current to the second diode.
11. A method for envelope detection comprising:
performing a DC level shift on an AC input signal such that a magnitude of the DC level shift is proportional to a peak envelope of the AC input signal, wherein said performing a DC level shift comprises charging a series capacitor and a shunt diode that receive the AC input signal;
coupling a second diode to the shunt diode;
applying a bias current to the shunt diode and a bias current to the second diode; and
selecting the second diode to be larger than the shunt diode.
12. The envelope detector of claim 1 , further comprising:
a second capacitor coupled between the second and the third nodes.
13. The envelope detector of claim 12 , further comprising:
a resistor between the second node and the second capacitor, wherein the second diode is larger than the shunt diode.
14. The method of claim 7 , further comprising:
coupling a second capacitor between the second and the third nodes.
15. The method of claim 14 , further comprising:
coupling a resistor between the second node and the second capacitor, wherein the second diode is larger than the shunt diode.