Field insulator FET device and fabrication method thereof
View Patent ↗A FinFET and a fabrication method thereof. The FinFET device includes an SOI substrate realized through a substrate, a buried oxide layer formed on the substrate, and a silicon epitaxial layer formed on predetermined areas of the buried oxide layer. A gate oxide layer is formed on the silicon epitaxial layer, and a gate electrode is formed on the gate oxide layer. A field insulator is formed on exposed areas of the buried oxide layer to thereby separate adjacent silicon epitaxial layers. Side surfaces of the silicon epitaxial layer are flattened through heat treatment. The fabrication method for a FinFET device includes forming the gate oxidation layer and the gate electrode on the SOI substrate; forming the mask pattern on the gate electrode; forming the trench by etching using the mask pattern as a mask; performing heat treatment to flatten the side surfaces of the silicon epitaxial layer; and forming the field insulator in the trench.
1. A method of fabricating a field insulator field effect transistor device, comprising:
sequentially forming a gate oxide layer, a polycrystalline silicon layer and a nitride layer on a silicon on insulator substrate, the silicon on insulator substrate including a silicon layer, a buried oxide layer, and a silicon epitaxial layer;
forming a mask pattern to pattern the nitride layer;
forming a trench by patterning the polycrystalline silicon layer, the gate oxide layer, and the silicon epitaxial layer using the patterned nitride layer as a mask;
performing a heat treatment to remove striations and facets formed on the etched side surface of the silicon epitaxial layer; and
forming a field insulator in the trench,
wherein the heat treatment is performed at a temperature of about 850° C. to about 1150° C. and in one of a hydrogen gas atmosphere and a heavy hydrogen gas atmosphere.
2. The fabrication method of claim 1 , wherein the heavy hydrogen gas atmosphere is a deuterium D 2 gas atmosphere.
3. The fabrication method of claim 1 , wherein the heat treatment is performed at a temperature in a range of about 1050° C. to about 1150° C.
4. The fabrication method of claim 1 , wherein striations and facets formed on the etched side surfaces of the silicon epitaxial layer are substantially removed by the heat treatment.
5. The fabrication method of claim 1 , wherein the mask pattern exposes the gate electrode at areas of a predetermined field region, which is a device isolation region.
6. The fabrication method of claim 1 , wherein forming the mask comprises:
forming a nitride layer on the gate electrode;
forming a photoresist pattern on the nitride layer that exposes the nitride layer at areas of a predetermined field region, which is a device isolation region; and
etching exposed portions of the nitride layer using the photoresist pattern as a mask, thereby forming a nitride layer pattern.
7. The fabrication method of claim 1 , wherein for forming the trench, dry etching is used to etch the exposed gate electrode, the gate oxide layer, and the silicon epitaxial layer.
8. The fabrication method of claim 1 , wherein for forming the trench, reactive ion etching is used to etch the exposed gate electrode, the gate oxide layer, and the silicon epitaxial layer.
9. The fabrication method of claim 1 , wherein for forming the field insulator in the trench comprises:
forming a field insulator on the exposed buried oxide layer through the trench and the mask pattern; and
performing chemical-mechanical polishing of the field insulator until the mask pattern is exposed.
10. The fabrication method of claim 1 , wherein a polycrystalline silicon layer is used as the gate electrode.