Transistor structure with stress modification and capacitive reduction feature in a width direction and method thereof
View Patent ↗A transistor comprises a source and drain positioned within an active region. A gate overlies a channel area of the active region, wherein the channel region separates the source and drain. The transistor further comprises at least one stress modifier and capacitive reduction feature extending from the source to the drain and underlying the gate for reducing capacitance associated with the gate, source and drain. The at least one stress modifier and capacitive reduction feature comprises dielectric and includes a shape defined at least partially by the active region.
1. A transistor comprising:
a source positioned within an active region;
a drain positioned within the active region;
a gate overlying a channel area of the active region, the channel region separating the source and drain; and
at least one stress modifier and capacitive reduction feature disposed within the active region, extending from the source to the drain, and underlying the gate for reducing capacitance associated with the gate, source and drain, wherein the at least one stress modifier and capacitive reduction feature comprises dielectric having a shape that is disposed within and defined at least partially by a portion of the active region corresponding to a previously removed portion of the active region.
2. The transistor of claim 1 wherein the at least one stress modifier and capacitive reduction feature further comprises a notch positioned around at least one side of the active area in close proximity to the gate.
3. The transistor of claim 2 wherein the notch is positioned on two opposing sides of the active area and substantially symmetric to the gate.
4. The transistor of claim 1 wherein the at least one stress modifier and capacitive reduction feature modifies stress in a width direction of the channel area.
5. The transistor of claim 1 wherein the width direction of the channel area is a <100> crystal orientation.
6. The transistor of claim 5 wherein the dielectric is one that exerts a compressive stress on the active region.
7. The transistor of claim 6 wherein the dielectric that exerts a compressive stress on the active region is an oxide.
8. The transistor of claim 1 wherein the width direction of the channel area is a <110> crystal orientation.
9. The transistor of claim 8 wherein the dielectric is one that exerts a tensile stress on the active region.
10. The transistor of claim 9 wherein the dielectric that exerts a tensile stress on the active region is silicon nitride.
11. The transistor of claim 1 wherein a total number of the at least one stress modifier and capacitive reduction feature is dependent on an overall width of the active region.
12. The transistor of claim 1 wherein the total number of the at least one stress modifier and capacitive reduction feature is further dependent on an optimum sub-width of the active region.
13. The transistor of claim 12 wherein the optimum sub-width is determined by a calculation of optimum performance metrics.
14. The transistor of claim 1 wherein the active region further comprises at least two stress modifying liners, a first liner surrounding at least a portion of a periphery of the active region and a second liner surrounding at least a portion of a surface of the at least one stress modifier and capacitive reduction feature.
15. The transistor of claim 14 wherein the second liner is substantially thicker in cross-sectional width than the first liner for exerting a substantially greater stress than the first liner.
16. The transistor of claim 14 wherein the first liner and the second liner further comprise an oxide.
17. The transistor of claim 1 further comprises at least two predetermined transistor building blocks, each of the at least two predetermined transistor building blocks having a sub-width and a side perimeter, wherein when any two of the at least two predetermined transistor building blocks are physically joined, the side perimeter thereof forms the at least one stress modifier and capacitive reduction feature.
18. The transistor of claim 17 wherein the active region further comprises at least two stress modifying liners, a first liner surrounding at least a portion of a periphery of the active region and a second liner surrounding at least a portion of a surface of the at least one stress modifier and capacitive reduction feature.
19. The transistor of claim 17 wherein the width direction of the channel area is a <100> crystal orientation.
20. The transistor of claim 19 wherein the dielectric is one that exerts a compressive stress on the active region.
21. The transistor of claim 20 wherein the dielectric that exerts a compressive stress on the active region is an oxide.
22. The transistor of claim 17 wherein the width direction of the channel area is a <110> crystal orientation.
23. The transistor of claim 22 wherein the dielectric is one that exerts a tensile stress on the active region.
24. The transistor of claim 23 wherein the dielectric that exerts a tensile stress on the active region is silicon nitride.
25. The transistor of claim 17 wherein the side perimeter of at least one of the two predetermined transistor building blocks further comprises a notch that determine in part the sub-width.
26. The transistor of claim 1 further comprising a plurality of transistors, each of the plurality of transistors having a structure of the transistor of claim 1 , the structure of the transistor of claim 1 being implemented in at least a majority of transistors of a predetermined conductivity type used to implement a non-memory function in an integrated circuit die.