Image sensor with improved dynamic range and method of formation
View Patent ↗Embodiments of the invention provide an image sensor having an improved dynamic range. A pixel cell comprises at least one transistor structure. The transistor structure comprises at least one semiconductor channel region, at least one gate for controlling the channel region, and first and second leads respectively coupled to a source region on one side of the at least one channel region and a drain region on an opposite side of the at least one channel region. The transistor structure has at least two threshold voltages associated with the at least one channel region, and an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.
1. A method of fabricating a transistor, the method comprising:
forming a semiconductor channel region;
forming a gate for controlling the channel region;
forming first and second leads respectively coupled to a source region on one side of the channel region and a drain region on an opposite side of the channel region; and
setting at least two threshold voltages associated with the channel region, one threshold voltage being in a sub-threshold region defined by another threshold voltage, wherein an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.
2. The method of claim 1 , wherein the transistor structure is formed as an active element for operating at least in part in a sub-threshold region.
3. The method of claim 1 , wherein the transistor structure is formed as a source follower transistor structure.
4. The method of claim 1 , wherein the act of forming the channel region comprises forming first, second, and third channel regions connected in parallel.
5. The method of claim 4 , wherein the act of setting the at least two threshold voltages comprises setting a highest first threshold voltage associated with the first channel region and setting second and third threshold voltages in the sub-threshold region defined by the first threshold voltage and associated with the second and third channel regions, respectively.
6. The method of claim 4 , wherein the act of setting the at least two threshold voltages comprises setting a highest first threshold voltage associated with the first channel region and setting a second threshold voltage in the sub-threshold region defined by the first threshold voltage and associated with the second and third channel regions.
7. The method of claim 1 , wherein the act of forming the channel region comprises forming one channel region having a normal conduction path and at least one parasitic conduction path.
8. The method of claim 7 , wherein the act of setting the at least two threshold voltages comprises setting a highest first threshold voltage associated with the normal conduction path and setting at least a second threshold voltage in the sub-threshold region defined by the first threshold voltage and associated with the at least one parasitic conduction path.
9. The method of claim 8 , wherein the act of forming the channel region comprises forming one channel region having first and second parasitic conduction paths, and wherein the act of setting the at least two threshold voltages comprises setting a second threshold voltage in the sub-threshold region defined by the first threshold voltage and associated with the first and second parasitic conduction paths.
10. The method of claim 8 , wherein the act of forming the channel region comprises forming one channel region having first and second parasitic conduction paths, and wherein the act of setting the at least two threshold voltages comprises setting second and third threshold voltages in the sub-threshold region defined by the first threshold voltage and associated with the first and second parasitic conduction paths, respectively.
11. The method of claim 1 , wherein the act of setting the two or more threshold voltages comprises forming the transistor structure having any of: two or more gate oxide thicknesses, two or more channel dopant concentrations, and two or more gate work-functions.
12. The method of claim 1 , wherein the act of setting the two or more threshold voltages comprises setting the two or more threshold voltages such that the I-V characteristic is such that the sub-threshold region and a linear region provide a same or similar amplification factor for a signal.
13. The method of claim 1 , further comprising forming a photo-conversion device.
14. The method of claim 13 , wherein the act of forming the photo-conversion device comprises forming a pinned photodiode.
15. A method of forming a pixel cell, the method comprising:
forming a photo-conversion device;
forming at least one transistor structure, wherein the at least one transistor structure is an active element for operating at least in part in a sub-threshold region, the act of forming the transistor structure comprising:
forming first, second, and third semiconductor channel regions;
forming at least one gate for controlling the channel regions;
forming first and second leads respectively coupled to source regions on one side of the channel regions and drain regions on an opposite side of the channel regions; and
setting at least two threshold voltages associated with the channel regions, wherein an I-V characteristic of the transistor structure is determined at least in part by the at least two threshold voltages.
16. The method of claim 15 , wherein the act of setting the at least two threshold voltages comprises setting a highest first threshold voltage associated with the first channel region and a second threshold voltage associated with the second and third channel regions.
17. The method of claim 15 , wherein the act of setting the at least two threshold voltages comprises setting a highest first threshold voltage associated with the first channel region and second and third threshold voltages associated with the second and third channel regions, respectively.
18. A method of forming a pixel cell, the method comprising:
forming a photo-conversion device; and
forming at least one transistor structure, wherein the at least one transistor structure is an active element for operating at least in part in a sub-threshold region, the act of forming the transistor structure comprising:
forming one semiconductor channel region having a normal conduction path and at least one parasitic conduction path;
forming a gate for controlling the channel region;
forming first and second leads respectively coupled to a source region on one side of the channel region and a drain region on an opposite side of the channel region;
setting a highest first threshold voltage associated with the normal conduction path; and
setting at least a second threshold voltage associated with the at least one parasitic conduction path, wherein an I-V characteristic of the transistor structure is determined at least in part by the threshold voltages.
19. The method of claim 18 , wherein the act of forming the channel region comprises forming first and second parasitic conduction paths, and wherein the act of setting the at least second threshold voltage comprises setting a second threshold voltage associated with the first and second conduction paths.
20. The method of claim 18 , wherein the act of forming the channel region comprises forming first and second parasitic conduction paths, and wherein the act of setting the at least second threshold voltage comprises setting second and third threshold voltages associated with the first and second conduction paths, respectively.