IP Library Granted Patent US 7,271,464
Granted Patent B2
US 7,271,464 · App. 10/925,715 · Granted Sep 18, 2007

Liner for shallow trench isolation

Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 7,271,464
App. No.
10/925,715
Granted
Sep 18, 2007
Kind
B2
Abstract

A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a silicon nitride barrier is deposited into the trench. The silicon nitride layer has a high nitrogen content near the trench walls to protect the walls. The silicon nitride layer further from the trench walls has a low nitrogen content and a high silicon content, to allow improved adhesion. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator. The resulting trench has a well-adhered insulator which helps the insulating properties of the trench.

Claims (30)

1. An isolation structure for an integrated circuit comprising:

a trench formed within a substrate, wherein the trench has a plurality of sidewalls and a base;

a silicon nitride layer within the trench defining a lined trench, the silicon nitride layer having silicon and nitrogen throughout the layer, wherein a portion of the silicon nitride layer at the sidewalls and base of the trench has a higher level of nitrogen than a portion of the silicon nitride layer most removed from the sidewalls and the base of the trench; and

an insulating material within the lined trench, wherein the insulating material is a spin-on dielectric.

2. The structure of claim 1 , further comprising an oxide layer between the sidewalls of the trench and the silicon nitride liner.

3. The structure of claim 1 , wherein the silicon nitride layer has a nitrogen content that is graded down from the sidewalls of the trench toward an interior portion of the trench.

4. The structure of claim 3 , wherein the silicon nitride layer has a linear nitrogen content gradient from the sidewalls and the base of the trench toward the interior portion of the trench.

5. The structure of claim 1 , wherein the silicon nitride layer comprises a plurality of layers, wherein each layer has a lower nitrogen content than a neighboring layer closer to the trench sidewalls.

6. The structure of claim 1 , wherein the insulating material is a non-conductive oxide material.

7. The structure of claim 6 , wherein the insulating material is a silicon oxide material.

8. The structure of claim 7 , further comprising a silicon oxynitride layer between the silicon nitride layer and the silicon oxide material.

9. An isolation structure for an integrated circuit comprising:

a trench formed within a substrate, wherein the trench has a plurality of sidewalls and a base;

a silicon nitride layer within the trench, wherein a portion of the silicon nitride layer at the sidewalls and base of the trench has a higher level of nitrogen than a portion of the silicon nitride layer most removed from the sidewalls and the base of the trench;

an insulating material within the trench, wherein the insulating material is a nonconductive silicon oxide material; and

a silicon oxynitride layer between the silicon nitride layer and the silicon oxide material, wherein the silicon oxynitride layer is between about 5 Å and 20 Å thick.

10. An isolation structure for an integrated circuit comprising:

a trench formed within a substrate, wherein the trench has a plurality of sidewalls and a base;

a silicon nitride layer within the trench defining a lined trench, the silicon nitride layer having silicon and nitrogen throughout the layer, wherein a portion of the silicon nitride layer at the sidewalls and base of the trench has a silicon content by weight of between about 48% and 64% and a higher level of nitrogen than a portion of the silicon nitride layer most removed from the sidewalls and the base of the trench; and

an insulating material within the lined trench, wherein the insulating material is a spin-on dielectric.

11. The structure of claim 10 , wherein the portion of the silicon nitride layer at the sidewalls and base of the trench has a silicon content by weight of between about 52% and 61%.

12. An isolation structure for an integrated circuit comprising:

a trench formed within a substrate, wherein the trench has a plurality of sidewalls and a base;

a silicon nitride layer within the trench, wherein a portion of the silicon nitride layer at the sidewalls and base of the trench has a higher level of nitrogen than a portion of the silicon nitride layer most removed from the sidewalls and the base of the trench, wherein the portion of the silicon nitride layer most removed from the sidewalls and the base of the trench has a silicon content by weight of between about 60% and 80%; and an insulating material within the trench.

13. The structure of claim 12 , further comprising an oxide layer between the sidewalls of the trench and the silicon nitride layer.

14. The structure of claim 12 , wherein the silicon nitride layer has a nitrogen content gradient from the sidewalls and the base of the trench toward the interior portion of the trench, the gradient being approximately linear.

15. The structure of claim 12 , wherein the silicon nitride layer comprises a plurality of layers, each layer having a lower nitrogen content than an adjacent layer closer to the sidewalls and base of the trench.

16. The structure of claim 12 , wherein the insulating material is a silicon oxide material.

17. The structure of claim 12 , wherein the insulating material is a spin-on dielectric.

18. The structure of claim 12 , further comprising a silicon oxynitride layer between the silicon nitride layer and the silicon oxide material.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2004
From: TRIVEDI, JIGISH D.; PATRAW, ROBERT D.; BEAMAN, KEVIN L.; SMYTHE, JOHN A. III
To: MICRON TECHNOLOGY, INC.
Reel/Frame 015736/0484 →
Continuity (1)
Related Publication 20060043521A1 · Mar 2, 2006