IP Library Granted Patent US 7,305,045
Granted Patent B2
US 7,305,045 · App. 10/926,212 · Granted Dec 4, 2007

Low voltage swing pad driver and receiver

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Quick Facts
Patent No.
US 7,305,045
App. No.
10/926,212
Granted
Dec 4, 2007
Kind
B2
Abstract

Low voltage swing pad driver and receiver. A transmitter portion and a receiver portion are implemented within various devices that communicate using low voltage swing pads communicatively coupled via a trace. The transmitter portion of one device generates a current signal that is pushed/pulled to a low voltage swing pad and is then passed across the trace to another low voltage swing pad. The transmitter portion includes a current driver that outputs the current signal to the low voltage swing pads, and the receiver portion includes a trans-impedance amplifier that transforms the received current signal into a voltage signal. The low voltage swing pad driver and receiver generates a relatively low voltage swing when compared to CMOS full-scale voltage swings thereby significantly reducing the possibility of introducing any noise and/or distortion of data that is communicated via the interface.

Claims (65)

1. An apparatus, comprising:

an integrated asynchronous digital subscriber line semiconductor chip that includes an analog front-end portion; and wherein:

the analog front-end portion includes a transmitter portion, the transmitter portion being communicatively coupled to a transmitter pad; and

the transmitter portion includes a voltage to current converter that is operable to convert a voltage signal to a current signal and to push/pull the current signal to the transmitter pad, from which the current signal is transmitted via a trace that is coupled to the transmitter pad.

2. The apparatus of claim 1 , wherein:

the current signal generated by the voltage to current converter of the transmitter includes a voltage swing less than approximately plus or minus 100 milli-Volts.

3. The apparatus of claim 1 , wherein:

the integrated asynchronous digital subscriber line semiconductor chip further includes a scrambler and a digital level converter;

the scrambler receives a digital input signal and then generates a scrambled digital input signal; and

the digital level converter converts a level of the scrambled digital input signal and provides the level convened scrambled digital input signal to the transmitter portion.

4. The apparatus of claim 3 , wherein:

a voltage level of the scrambled digital input signal is approximately 1.8 Volts; and

a voltage level of the level converted scrambled digital input signal that is provided to the transmitter portion is approximately 3.3 Volts.

5. The apparatus of claim 1 , wherein:

the transmitter pad communicatively couples to another device via the trace.

6. An apparatus, comprising:

an integrated asynchronous digital subscriber line semiconductor chip that includes an analog front-end portion; and wherein:

the analog front-end portion includes a receiver portion, the receiver portion being communicatively coupled to a receiver pad;

the receiver portion includes a current to voltage converter that is operable to receive a current signal from the receiver pad and to transform the received current signal to a voltage signal; and

the current signal is received at the receiver pad via a trace that couples to the receiver pad.

7. The apparatus of claim 6 , wherein:

the current signal received by the current to voltage convener of the receiver portion includes a voltage swing less than approximately plus or minus 100 milli-Volts.

8. The apparatus of claim 6 , wherein:

the receiver portion includes a digital level converter that is operable to convert the voltage signal from a first level to a second level; and

the first level has a voltage of approximately 3.3 Volts and the second level has a voltage of approximately 1.8 Volts.

9. The apparatus of claim 6 , wherein:

the receiver portion includes a trans-impedance amplifier that is operable to receive the current signal and to transform the received current signal to the voltage signal; and

the voltage signal has a magnitude that is approximately 3.3 Volts.

10. The apparatus of claim 6 , wherein:

the integrated asynchronous digital subscriber line semiconductor chip further includes a de-scrambler and a digital level converter;

the receiver portion provides the digital signal to the digital level converter;

the digital level converter receives the digital signal and changes a level of the digital signal; and

the de-scrambler receives the voltage level changed digital signal and then generates a de-scrambled digital output signal.

11. An apparatus, comprising:

a transmitter portion;

a transmitter pad that is communicatively coupled to the transmitter portion; and

wherein:

the transmitter portion includes a voltage to current converter that is operable to convert a voltage signal to a current signal and to push/pull the current signal to the transmitter pad, from which the current signal is transmitted via a trace that is coupled to the transmitter pad.

12. The apparatus of claim 11 , wherein:

the current signal generated by the voltage to current converter of the transmitter portion includes a voltage swing less than approximately plus or minus 100 milli-Volts.

13. The apparatus of claim 11 , wherein:

the semiconductor system further includes a scrambler and a digital level converter;

the scrambler receives a digital input signal and then generates a scrambled digital input signal; and

the digital level convener converts a level of the scrambled digital input signal and provides the level converted scrambled digital input signal to the transmitter portion.

14. The apparatus of claim 11 , wherein:

the transmitter portion further includes a plurality of switches;

the controlling of the plurality of switches controls the pushing and pulling of the current signal to the transmitter pad.

15. The apparatus of claim 11 , wherein:

the transmitter pad is communicatively coupled to a receiver pad via the trace.

16. An apparatus, comprising:

a receiver portion;

a receiver pad that is communicatively coupled to the receiver portion; and

wherein:

the receiver portion includes a current to voltage converter that is operable to receive a current signal from the receiver pad and to transform the received current signal to a voltage signal; and

the current signal is received at the receiver pad via a trace that couples to the receiver pad.

17. The apparatus of claim 16 , wherein:

the current signal received by the current to voltage converter of the receiver portion includes a voltage swing less than approximately plus or minus 100 milli-Volts.

18. The apparatus of claim 16 , wherein:

the receiver portion includes a digital level convener that is operable to convert the voltage signal from a first level to a second level; and

the first level has a voltage of approximately 3.3 Volts and the second level has a voltage of approximately 1.8 Volts.

19. The apparatus of claim 16 , wherein:

the receiver portion includes a trans-impedance amplifier that is operable to receive the current signal and to transform the received current signal to the voltage signal; and

the voltage signal has a magnitude that is approximately 3.3 Volts.

20. The apparatus of claim 16 , wherein:

the receiver pad is communicatively coupled to a transmitter pad via the trace.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERROR IN RECORDING THE MERGER PREVIOUSLY RECORDED AT REEL: 047357 FRAME: 0302. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048674/0834 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER PREVIOUSLY RECORDED ON REEL 047195 FRAME 0658. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047357/0302 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047195/0658 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →