One-transistor composite-gate memory
View Patent ↗One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold voltages may be assigned a data value, providing the ability to store one or more bits of data in a single memory cell. To control the threshold voltage, the oxygen vacancies may be manipulated by trapping electrons within the vacancies, freeing trapped electrons from the vacancies, moving the vacancies within the trapping layer and annihilating the vacancies.
1. A one-transistor nonvolatile memory cell, comprising:
a gate dielectric layer overlying a semiconductor substrate;
a trapping layer overlying the gate dielectric layer and capable of manipulation of oxygen vacancies to adjust the threshold voltage of the memory cell;
a control gate layer overlying and adjoining the trapping layer;
a first source/drain region formed in the substrate on a first side of the gate dielectric layer; and
a second source/drain region formed in the substrate on a second, opposite side of the gate dielectric layer.
2. The memory cell of claim 1 , wherein the trapping layer comprises at least one material selected from the group consisting of aluminum oxides, hafnium oxide, zirconium oxides, titanium oxides, hafnium silicate, zirconium silicate, tantalum oxide, barium strontium titanate and lead zirconium titanate.
3. The memory cell of claim 2 , wherein the at least one material is either amorphous or crystalline.
4. The memory cell of claim 1 , wherein the trapping layer is overlying and adjoining the gate dielectric layer.
5. The memory cell of claim 1 , wherein the control gate layer comprises an oxygen-rich conductive metal oxide.
6. The memory cell of claim 1 , wherein the trapping layer is formed to have a predetermined level of oxygen vacancies.
7. The memory cell of claim 1 , wherein the gate dielectric layer comprises at least one material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides.
8. A one-transistor nonvolatile memory cell, comprising:
a gate dielectric layer overlying and adjoining a semiconductor substrate;
a trapping layer, overlying and adjoining the gate dielectric layer, capable of manipulation of oxygen vacancies to adjust the threshold voltage of the memory cell;
a control gate layer overlying and adjoining the trapping layer;
a first source/drain region formed in the substrate on a first side of the gate dielectric layer; and
a second source/drain region formed in the substrate on a second, opposite side of the gate dielectric layer.
9. The memory cell of claim 8 , wherein the trapping layer is formed to have a predetermined level of oxygen vacancies.
10. The memory cell of claim 8 , wherein the control gate layer comprises an oxygen-rich conductive metal oxide.
11. The memory cell of claim 8 , wherein the trapping layer comprises at least one material selected from the group consisting of aluminum oxides, hafnium oxide, zirconium oxides, titanium oxides, hafnium silicate, zirconium silicate, tantalum oxide, barium strontium titanate and lead zirconium titanate.
12. The memory cell of claim 8 , wherein the gate dielectric layer comprises at least one material selected from the group consisting of silicon oxides, silicon nitrides and silicon oxynitrides.
13. A nonvolatile memory device, comprising:
a memory array arranged in rows and columns, each row of cells coupled by a wordline and each column of cells coupled by a bitline, wherein at least one memory cell of the array is a one-transistor memory cell comprising:
a gate dielectric layer overlying a semiconductor substrate;
a trapping layer overlying the gate dielectric layer and capable of manipulation of oxygen vacancies to adjust the threshold voltage of the at least one memory cell;
a control gate layer overlying and adjoining the trapping layer;
a first source/drain region formed in the substrate on a first side of the gate dielectric layer; and
a second source/drain region formed in the substrate on a second, opposite side of the gate dielectric layer.
14. The memory device of claim 13 , wherein the memory device is a NOR memory device with the memory array arranged in a NOR architecture.
15. The memory device of claim 13 , wherein the memory device is a NAND memory device with the memory array arranged in a NAND architecture.
16. An electronic system, comprising:
a processor; and
one or more memory devices coupled to the processor, wherein at least one of the memory devices comprises:
an array of memory cells arranged in rows and columns, each row of cells coupled by a wordline and each column of cells coupled by a bitline wherein at least one memory cell of the array of memory cells is a one-transistor memory cell comprising:
a gate dielectric layer overlying a semiconductor substrate;
a trapping layer overlying the gate dielectric layer and capable of manipulation of oxygen vacancies to adjust the threshold voltage of the memory cell;
a control gate layer overlying and adjoining the trapping layer;
a first source/drain region formed in the substrate on a first side of the gate dielectric layer; and
a second source/drain region formed in the substrate on a second, opposite side of the gate dielectric layer.
17. The electronic system of claim 16 , wherein the memory device is coupled to receive commands from the processor for accessing one or more of the memory cells of the array of memory cells.