Content addressable memory (CAM) devices that support power saving longest prefix match operations and methods of operating same
Content addressable memory (CAM) devices include at least one CAM array having a plurality of columns of ternary CAM cells therein. A bit/data line driver circuit, which receives search words and write words, is electrically coupled to the CAM array. The bit/data line driver circuit is configured to save power by logically combining incoming search words with a global mask that designates locations of active ones of the plurality of columns having exclusively locally masked CAM cells at valid entries therein. The bit/data line driver circuit includes a global mask generator configured to receive write words to be added to the CAM array during respective write operations.
1. A content addressable memory device, comprising:
a CAM array having a plurality of active columns of ternary CAM cells therein; and
a bit/data line driver circuit electrically coupled to said CAM array, said bit/data line driver circuit configured to apply an LPM-specific mask to incoming search words so that each of the plurality of active columns of ternary CAM cells having exclusively locally masked data in valid entry locations is globally masked during search operations.
2. The content addressable memory device of claim 1 , wherein said bit/data line driver circuit comprises an LPM-specific global mask generator configured to receive write words to be added to said CAM array during respective write operations.
3. The content addressable memory device of claim 2 , wherein said LPM-specific global mask generator comprises an LPM-specific global mask register configured to store the LPM-specific mask.
4. The content addressable memory device of claim 3 , wherein said LPM-specific global mask generator comprises a local mask decoder configured to receive the write words to be added to said CAM array.
5. The content addressable memory device of claim 1 , wherein said CAM array comprises a segmented sub-array of dedicated XY mask cells configured to retain two global mask bits per mask cell and a segmented sub-array of XY CAM cells therein.
6. The content addressable memory device of claim 5 , wherein the segmented sub-array of dedicated XY mask cells comprises a mask assertion circuit electrically coupled to said a bit/data line driver circuit, said mask assertion circuit configured to pass global mask signals to said bit/data line driver circuit in response to a read mask operation.
7. A content addressable memory device, comprising:
a CAM array having a plurality of active columns of ternary CAM cells therein; and
a bit/data line driver circuit electrically coupled to said CAM array, said bit/data line driver circuit configured to apply a BM-specific mask to incoming search words so that each of the plurality of active columns of ternary CAM cells having exclusively locally masked data in valid entry locations is globally masked during search operations.
8. The content addressable memory device of claim 7 , wherein said bit/data line driver circuit comprises a global mask generator configured to receive write words to be added to said CAM array during respective write operations.
9. The content addressable memory device of claim 8 , wherein said global mask generator comprises a global mask register configured to store the BM-specific mask.
10. The content addressable memory device of claim 9 , wherein said global mask generator comprises a local mask decoder configured to receive the write words to be added to said CAM array.
11. The content addressable memory device of claim 7 , wherein said CAM array comprises a segmented sub-array of dedicated XY mask cells configured to retain two global mask bits per mask cell.
12. The content addressable memory device of claim 11 , wherein the segmented sub-array of dedicated XY mask cells comprises a mask assertion circuit electrically coupled to said a bit/data line driver circuit, said mask assertion circuit configured to pass global mask signals to said bit/data line driver circuit in response to a read mask operation.
13. A content addressable memory device, comprising:
a CAM array having a plurality of columns of ternary CAM cells therein; and
a bit/data line driver circuit electrically coupled to said CAM array, said bit/data line driver circuit configured to logically combine incoming search words with a global mask that designates locations of active ones of the plurality of columns having exclusively locally masked CAM cells at valid entries in said CAM array.
14. The content addressable memory device of claim 13 , wherein said bit/data line driver circuit comprises a global mask generator configured to receive write words to be added to said CAM array during respective write operations.
15. The content addressable memory device of claim 14 , wherein said global mask generator comprises a global mask register configured to store the global mask.
16. The content addressable memory device of claim 15 , wherein said global mask generator comprises a local mask decoder configured to receive the write words to be added to said CAM array.
17. The content addressable memory device of claim 13 , wherein said CAM array comprises a segmented sub-array of dedicated XY mask cells configured to retain two global mask bits per mask cell.
18. The content addressable memory device of claim 17 , wherein the segmented sub-array of dedicated XY mask cells comprises a mask assertion circuit electrically coupled to said a bit/data line driver circuit, said mask assertion circuit configured to pass global mask signals to said bit/data line driver circuit in response to a read mask operation.
19. A method of operating an integrated circuit device, comprising:
generating a mask value that designates locations of active ones of a plurality of columns of a CAM array having exclusively locally masked CAM cells at valid entries in the CAM array.
20. The method of claim 19 , further comprising the step of:
updating a value of the global mask in response to writing an entry into the CAM array.
21. A content addressable memory (CAM) block, comprising logic configured to perform the following operation:
generating a mask value that designates locations of active ones of a plurality of columns of CAM cells in the CAM array block having exclusively locally masked CAM cells at valid entries in the CAM array block.
22. A content addressable memory device, comprising:
a CAM array having a plurality of active columns of ternary CAM cells therein; and
a bit/data line driver circuit electrically coupled to said CAM array, said bit/data line driver circuit configured to apply a mask to incoming search words so that at least one pair of differential data lines associated with an active column of ternary CAM cells having exclusively locally masked data in valid entry locations is globally masked, floated or frozen during consecutive search operations.