Deposition of hard-mask with minimized hillocks and bubbles
For forming an IC (integrated circuit) structure over a conductive surface, a hard-mask is deposited on the conductive surface with a low temperature in a range of from about 220° Celsius to about 320° Celsius for minimized formation of hillocks. Generally, formation of hillocks and bubbles from deposition of the hard-mask are minimized on the conductive surface. The hard-mask is etched away from the conductive surface, and the IC structure is formed over the conductive surface after the hard-mask is etched away.
1 . A method for forming an IC (integrated circuit) structure, comprising:
A. depositing a hard-mask on a conductive surface with a low temperature in a range of from about 220° Celsius to about 320° Celsius for minimized formation of hillocks;
B. etching away the hard-mask from the conductive surface; and
C. forming the IC structure over the conductive surface after step B.
2 . The method of claim 1 , wherein the conductive surface is a copper or copper alloy surface, and wherein the hard-mask is a silicon nitride (SiN) hard-mask.
3 . The method of claim 2 , wherein the SiN hard-mask is deposited in an ULDR (ultra low deposition rate) PECVD (plasma enhanced chemical vapor deposition) process.
4 . The method of claim 3 , wherein the SiN hard-mask has a thickness in a range of from about 80 Å to about 120 Å.
5 . The method of claim 3 , wherein the ULDR PECVD process includes the steps of:
flowing NH 3 at a flow rate in a range of from about 600 sccm to about 1,000 sccm;
flowing SiH 4 at a flow rate in a range of from about 65 sccm to about 135 sccm;
setting a pressure to be in a range of from about 1 Torr to about 2 Torr;
setting a temperature to be in a range of from about 220° Celsius to about 320° Celsius;
applying HF (high frequency) power in a range of from about 300 watts to about 400 watts on a plasma electrode; and
applying LF (high frequency) power in a range of from about 100 watts to about 200 watts on a wafer chuck.
6 . The method of claim 2 , further including the step of:
applying dual powers including HF (high frequency) power applied on a plasma electrode and LF (low frequency) power applied on a heater block during deposition of the SiN hard-mask that is compressive.
7 . The method of claim 2 , further comprising:
performing a temperature soak at a temperature in a range of from about 220° Celsius to about 320° Celsius, before step A.
8 . The method of claim 7 , wherein the temperature soak is performed for a short time period in a range of from about 2 seconds to about 5 seconds.
9 . The method of claim 7 , further comprising:
minimizing bubble formation in the SiN hard-mask by pre-treating the copper or copper alloy surface with hydrogen based plasma, after the temperature soak.
10 . The method of claim 9 , wherein the pre-treatment of the copper or copper alloy surface is performed for a short time period in a range of from about 2 seconds to about 5 seconds.
11 . The method of claim 10 , wherein the pre-treatment of the copper or copper alloy surface includes the steps of:
flowing NH 3 at a flow rate in a range of from about 600 sccm to about 1,000 sccm;
setting a pressure to be in a range of from about 1 Torr to about 2 Torr;
setting a temperature to be in a range of from about 220° Celsius to about 320° Celsius; and
applying HF (high frequency) power in a range of from about 300 watts to about 400 watts on a plasma electrode.
12 . The method of claim 2 , wherein the IC structure is comprised of polymer layers formed from the copper or copper alloy surface to form a polymer memory cell in a BEOL (back end of line) process.
13 . The method of claim 2 , wherein the IC structure is a diffusion barrier structure formed over the copper or copper alloy surface.
14 . The method of claim 13 , wherein the diffusion barrier structure is a tantalum cap.
15 . The method of claim 1 , wherein the IC structure is comprised of polymer layers formed from the conductive surface to form a polymer memory cell in a BEOL (back end of line) process.
16 . The method of claim 1 , wherein the IC structure is a diffusion barrier structure formed over the conductive surface.
17 . The method of claim 16 , wherein the diffusion barrier structure is a tantalum cap.
18 . The method of claim 1 , further comprising:
performing a temperature soak at a temperature in a range of from about 220° Celsius to about 320° Celsius, before step A.
19 . The method of claim 18 , wherein the temperature soak is performed for a short time period in a range of from about 2 seconds to about 5 seconds.
20 . The method of claim 18 , further comprising:
minimizing bubble formation in the hard-mask by pre-treating the conductive surface with hydrogen based plasma, after the temperature soak.
21 . The method of claim 20 , wherein the pre-treatment of the conductive surface is performed for a short time period in a range of from about 2 seconds to about 5 seconds.
22 . A method for forming an IC (integrated circuit) structure over a conductive surface, comprising:
A. performing a temperature soak at a temperature in a range of from about 220° Celsius to about 320° Celsius for a short time period in a range of from about 2 seconds to about 5 seconds;
B. pre-treating the conductive surface with a hydrogen based plasma for a short time period in a range of from about 2 seconds to about 5 seconds;
C. depositing a silicon nitride (SiN) hard-mask on the conductive surface with a low temperature in a range of from about 220° Celsius to about 320° Celsius for minimized formation of hillocks during an ULDR (ultra low deposition rate) PECVD (plasma enhanced chemical vapor deposition) process;
D. applying dual powers including HF (high frequency) power applied on the plasma electrode and LF (low frequency) power applied on a heater block for deposition of the SiN hard-mask that is compressive;
E. etching away the SiN hard-mask from the conductive surface; and
F. forming the IC structure over the conductive surface.
23 . A method for forming an IC (integrated circuit) structure over a copper or copper alloy surface, comprising:
A. performing a temperature soak at a temperature in a range of from about 220° Celsius to about 320° Celsius for a short time period in a range of from about 2 seconds to about 5 seconds;
B. pre-treating the copper or copper alloy surface with a hydrogen based plasma for a short time period in a range of from about 2 seconds to about 5 seconds, including the steps of:
flowing NH 3 at a flow rate in a range of from about 600 sccm to about 1,000 sccm;
setting a pressure to be in a range of from about 1 Torr to about 2 Torr;
setting a temperature to be in a range of from about 220° Celsius to about 320° Celsius; and
applying HF (high frequency) power in a range of from about 300 watts to about 400 watts on a plasma node;
C. depositing a silicon nitride (SiN) hard-mask on the copper or copper alloy surface with a low temperature in a range of from about 220° Celsius to about 320° Celsius for minimized formation of hillocks on the copper or copper alloy surface during an ULDR (ultra low deposition rate) PECVD (plasma enhanced chemical vapor deposition) process that includes the steps of:
flowing NH 3 at a flow rate in a range of from about 600 sccm to about 1,000 sccm;
flowing SiH 4 at a flow rate in a range of from about 65 sccm to about 135 sccm;
setting a pressure to be in a range of from about 1 Torr to about 2 Torr;
setting a temperature to be in a range of from about 220° Celsius to about 320° Celsius;
applying a HF (high frequency) power in a range of from about 300 watts to about 400 watts on a plasma electrode; and
applying a LF (low frequency) power in a range of from about 100 watts to about 200 watts on a wafer chuck;
wherein the SiN hard-mask that is compressive is deposited to a thickness in a range of from about 80 Å to about 120 Å;
D. etching away the SiN hard-mask from the copper or copper alloy surface; and
E. forming the IC structure over the copper or copper alloy surface, wherein the IC structure is one of a tantalum cap or polymer layers of a polymer memory cell in a BEOL (back end of line) process.