Programmable gain amplifier with glitch minimization
View Patent ↗A programable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a resistor that is connected to a reference voltage and multiple parallel taps that tap off the resistor. A two-stage switch network having fine stage switches and coarse stage switches connects the resistor taps to an output node of the PGA. The taps and corresponding fine stage switches are arranged into two or more groups, where each group has n-number of fine stage switches and corresponding taps. One terminal of each fine stage switch is connected to the corresponding resistor tap, and the other terminal is connected to an output terminal for the corresponding group. The coarse stage switches select from among the groups of fine stage switches, and connect to the output of the PGA. During operation, one selected tap is connected to the output of the PGA by closing the appropriate fine stage switch and coarse stage switch, where the selected tap defines a selected group of the fine stage switches. Additionally, one fine stage switch is closed in each of the non-selected groups of fine stage switches. In one embodiment, the location of the closed switches in the non-selected groups is the mirror image of the location in an adjacent group. This reduces the transient voltages that occur when tap selection changes from one group to another.
1. A programmable gain amplifier (PGA), comprising:
a resistor having first adjacent taps and second adjacent taps;
first switching means for switchably coupling the first adjacent taps to a first output terminal;
second switching means for switchably coupling the second adjacent taps to a second output terminal; and
third switching means for switchably coupling the first output terminal and the second output terminal to a third output terminal;
wherein the second switching means electrically couples a tap of the second adjacent taps to the second output terminal when the first switching means electrically couples a tap of the first adjacent taps to the first output terminal.
2. The PGA of claim 1 , further comprising an amplifier having an output coupled to an input of the resistor.
3. The PGA of claim 2 , wherein the resistor, the first switching means, the second switching means, the third switching means, and the amplifier have a common substrate.
4. The PGA of claim 1 , wherein the resistor is connected to a reference voltage.
5. The PGA of claim 1 , wherein if an nth switch of the first switching means is closed, then an nth switch of the second switching means is closed.
6. The PGA of claim 1 , wherein if an nth switch of the first switching means is closed, then an [(m+1)−nth] switch of the second switching means is closed, and wherein m is a number of switches in the first or second switching means.
7. The PGA of claim 1 , wherein the third switching means electrically couples the first output terminal to the third output terminal, and wherein the second switching means electrically couples the tap of the second adjacent taps to the second output terminal to pre-charge a parasitic capacitance of the second switching means.
8. The PGA of claim 1 , wherein the resistor, the first switching means, the second switching means, and the third switching means have a common substrate.
9. The PGA of claim 8 , wherein said common substrate is a CMOS substrate.
10. A programmable gain amplifier (PGA), comprising:
a resistor having a first plurality of adjacent taps and a second plurality of adjacent taps;
a first plurality of switches having input terminals corresponding to the first plurality of adjacent taps and having a first output terminal;
a second plurality of switches having input terminals corresponding to the second plurality of adjacent taps and having a second output terminal; and
switching means for switchably coupling the first output terminal and the second output terminal to a third output terminal;
wherein a switch of the second plurality of switches electrically couples a tap of the second plurality of adjacent taps to the second output terminal when a switch of the first plurality of switches electrically couples a tap of the first plurality of adjacent taps to the first output terminal.
11. The PGA of claim 10 , further comprising an amplifier having an output coupled to an input of the resistor.
12. The PGA of claim 11 , wherein the resistor, the first plurality of switches, the second plurality of switches, the switching means, and the amplifier have a common substrate.
13. The PGA of claim 10 , wherein the resistor is connected to a reference voltage.
14. The PGA of claim 10 , wherein if an nth switch of the first plurality of switches is closed, then an nth switch of the second plurality of switches is closed.
15. The PGA of claim 10 , wherein if an nth switch of the first plurality of switches is closed, then an [(m+1)−nth] switch of the second plurality of switches is closed, and wherein m is a number of switches in the first or second plurality of switches.
16. The PGA of claim 10 , wherein the switching means electrically couples the first output terminal to the third output terminal, and wherein the switch of the second plurality of switches electrically couples the tap of the second plurality of adjacent taps to the second output terminal to pre-charge a parasitic capacitance of the switch of the second plurality of switches.
17. The PGA of claim 10 , wherein the resistor, the first plurality of switches, the second plurality of switches, and the switching means have a common substrate.
18. The PGA of claim 17 , wherein said common substrate is a CMOS substrate.
19. The PGA of claim 3 , wherein said common substrate is a CMOS substrate.
20. The PGA of claim 12 , wherein said common substrate is a CMOS substrate.