IP Library Granted Patent US 7,643,665
Granted Patent B2
US 7,643,665 · App. 10/929,798 · Granted Jan 5, 2010

Method of design analysis of existing integrated circuits

Assignee: Semiconductor Insights Inc.
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Quick Facts
Patent No.
US 7,643,665
App. No.
10/929,798
Granted
Jan 5, 2010
Kind
B2
Abstract

The present invention involves a computationally efficient method of determining the locations of standard cells in an image of an IC layout. The initial step extracts and characterizes points of interest of the image. A coarse localization of possible standard cell locations is performed and is based on a comparison of the points of interest of an instance of an extracted standard cell and the remaining points of interest in the image. A more rigid comparison is made on the list of possible locations comprising a coarse match and a fine match. The coarse match results in a shortlist of possible locations. The fine match performs comparisons between the template and the shortlist. Further filtering is done to remove the effects of noise and texture variations and statistics on the results are generated to achieve the locations of the standard cells on the IC layout.

Claims (38)

1. A method of determining high probability locations of standard cells in an image of an IC layout comprising:

extracting and characterizing features of the IC layout;

extracting a standard cell from the IC layout and using the standard cell as a template for comparison;

obtaining a coarse localization of possible locations of standard cells by comparing characterizing features of the template with characterizing features of the remainder of the IC layout; and

applying a fine filter to said possible locations to obtain said high probability locations.

2. A method as claimed in claim 1 comprising:

applying a coarse filter to said possible locations to obtain coarse filtered possible locations, wherein the fine filter is applied to said coarse filtered possible locations to obtain said high probability locations.

3. A method as claimed in claim 1 wherein obtaining a coarse localization of possible locations of standard cells comprises:

comparing said features from the first instance of a standard cell to said features of the image to identify similar features;

casting votes on the similar features to show the level of confidence on the similarity of the similar features; and

computing the weight of the votes and determining possible matches by locations on the image showing high weights.

4. A method as claimed in claim 1 wherein the application of the fine filter comprises:

computing gradients for the template and a possible location from the set of possible locations;

computing a first set of dot products of the gradients;

applying morphological dilation of the first set of dot products to obtain a second set of dot products;

determining order statistics on the second set of dot products; and

determining if the order statistics are below a predefined threshold, wherein if the order statistics are less than the predefined threshold, the possible location is one of said high probability locations.

5. A method as claimed in claim 1 wherein the characterizing features comprise points of interest on a first conductive layer of the IC.

6. A method as claimed in claim 5 wherein the points of interest are selected from centers of contacts on the first conductive layer, centers of vias on the first conductive layer and corners of polygons representing the first conductive layer.

7. Apparatus for determining high probability locations of standard cells in an image of an IC layout comprising:

a processor having access to said image and comprising:

means for extracting and characterizing features of the IC layout;

means for creating a symbolic representation of a standard cell from the IC layout and using the standard cell as a template for comparison;

means for obtaining a coarse localization of possible locations of standard cells by comparing characterizing features of the template with characterizing features of the remainder of the IC layout; and

means for applying a fine filter to said possible locations to obtain said high probability locations.

8. Apparatus as claimed in claim 7 wherein the means for obtaining a coarse localization of possible locations of standard cells comprises:

means for comparing said features from the first instance of a standard cell to said features of the image to identify similar features;

means for casting votes on the similar features to show the level of confidence on the similarity of the similar features; and

computing the weight of the votes and determining possible matches by locations on the image showing high weights.

9. Apparatus as claimed in claim 7 wherein the fine filter means comprises:

means for computing gradients for the template and a possible location from the set of possible locations;

means for computing a first set of dot products of the gradients;

means for applying morphological dilation of the first set of dot products to obtain a second set of dot products;

means for determining order statistics on the second set of dot products; and

means for determining if the order statistics are below a predefined threshold, wherein if the order statistics are less than the predefined threshold, the possible location is one of said high probability locations.

10. Apparatus as claimed in claim 7 wherein the characterizing features comprise points of interest on a first conductive layer of the IC.

11. Apparatus as claimed in claim 7 , said processor further comprising means for applying a coarse filter to the possible locations to obtain coarse filtered possible locations, wherein said means for applying a fine filter is applied to said course filtered possible locations to obtain said high probability locations.

12. Apparatus as claimed in claim 10 , wherein the points of interest are selected from centers of contacts on the first conductive layer, centers of vias on the first conductive layer and corners of polygons representing the first conductive layer.

Assignments (5)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2021
From: STELLUS CAPITAL INVESTMENT CORPORATION, AS ADMINISTRATIVE AGENT
To: TECHINSIGHTS INC.
Reel/Frame 058096/0558 →
SECURITY INTEREST Recorded Nov 10, 2021
From: TECHINSIGHTS INC.; VLSI RESEARCH INC.
To: CAPITAL ONE, NATIONAL ASSOCIATION
Reel/Frame 058096/0721 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Aug 16, 2017
From: TECHINSIGHTS INC.
To: STELLUS CAPITAL INVESTMENT CORPORATION, AS ADMINISTRATIVE AGENT
Reel/Frame 043571/0385 →
CHANGE OF NAME Recorded Oct 9, 2014
From: SEMICONDUCTOR INSIGHTS INC.
To: TECHINSIGHTS INC.
Reel/Frame 033941/0692 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2005
From: ZAVADSKY, VYACHESLAV L.; GONT, VAL; KEYES, EDWARD; ABT, JASON; BEGG, STEPHEN
To: SEMICONDUCTOR INSIGHTS INC.
Reel/Frame 016224/0676 →
Continuity (1)
Related Publication 20060045325A1 · Mar 2, 2006