Devices with HfSiON dielectric films which are Hf-O rich
View Patent ↗A dielectric film containing atomic layer deposited HfSiON and a method of fabricating such a dielectric film produce a reliable dielectric layer having an equivalent oxide thickness thinner than attainable using SiO 2 . The HfSiON layer thickness is controlled by repeating for a number of cycles a sequence including pulsing a hafnium containing precursor into a reaction chamber, pulsing an oxygen containing precursor into the reaction chamber, pulsing a silicon containing precursor into the reaction chamber, and pulsing a nitrogen containing precursor until a desired thickness is formed. Dielectric films containing atomic layer deposited HfSiON are thermodynamically stable such that the HfSiON will have minimal reactions with a silicon substrate or other structures during processing.
1. An electronic device comprising:
a substrate; and
a dielectric layer on the substrate, the dielectric layer containing a HfSiON layer, the HfSiON layer structured as one or more monolayers; and
a transition region between the substrate and the HfSiON layer such the transition region is a graded material region from the substrate to the HfSiON layer wherein the HfSiON layer is rich in Hf—O.
2. The electronic device of claim 1 , wherein the dielectric layer is substantially amorphous.
3. The electronic device of claim 1 , wherein the dielectric layer has a thickness ranging from about 1 nm to 3 nm.
4. The electronic device of claim 1 , wherein the dielectric layer is a dielectric material of a capacitor in the electronic device.
5. The electronic device of claim 1 , wherein the dielectric layer is a gate dielectric of a transistor in the electronic device.
6. The electronic device of claim 1 , wherein the dielectric layer is a gate dielectric disposed in a memory of the electronic device.
7. The electronic device of claim 1 , wherein the electronic device is adapted into an electronic system.
8. A capacitor, comprising:
a first conductive layer on a substrate;
a dielectric layer containing a HfSiON layer, the HfSiON layer structured as one or more monolayers, the dielectric layer disposed on the first conductive layer;
a transition region between the first conductive layer and the HfiSiON layer such the transition region is a graded material region from the first conductive layer to the HfSiON layer; and
a second conductive layer disposed on the dielectric layer wherein the HfSiON layer is rich in Hf—O.
9. The capacitor of claim 8 , wherein the dielectric layer is substantially amorphous.
10. The capacitor of claim 8 , wherein the dielectric layer exhibits a dielectric constant in the range from about 7 to about 14.
11. A transistor comprising:
a body region in a substrate between a source region and a drain region;
a dielectric film containing a HfSiON layer disposed on the body region between a source region and a drain region, the HfSiON layer structured as one or more monolayers;
a transition region between the body region and the HfSiON layer such the transition region is a graded material region from the body region to the HfSiON layer wherein the HfSiON layer is rich in Hf—O; and
a gate coupled to the dielectric film.
12. The transistor of claim 11 , wherein the dielectric film is substantially amorphous.
13. The transistor of claim 11 , wherein the dielectric film exhibits a dielectric constant in the range from about 9 to about 14.
14. The transistor of claim 11 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) in the range from about 3 Angstroms to about 13 Angstroms.
15. The transistor of claim 11 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.
16. A transistor comprising:
a body region in a substrate between a source region and a drain region;
a gate dielectric disposed on the body region;
a floating gate disposed on the gate dielectric;
a control gate; and
a floating gate dielectric interposed between the floating gate and the control gate, wherein at least one of the gate dielectric or the floating gate dielectric includes a dielectric film containing a HfSiON layer, the HfSiON layer structured as one or more monolayers; and
a transition region between the HfSiON layer and a transistor region on which the dielectric film is disposed such the transition region is a graded material region from the transistor region to the HfSiON layer wherein the HfSiON layer is rich in Hf—O.
17. The transistor of claim 16 , wherein the gate dielectric includes the dielectric film containing the HfSiON layer.
18. The transistor of claim 16 , wherein the floating gate dielectric includes the dielectric film containing the HfSiON layer.
19. The transistor of claim 16 , wherein the dielectric film is substantially amorphous.
20. The transistor of claim 16 , wherein the dielectric film exhibits a dielectric constant in the range from about 9 to about 14.
21. The transistor of claim 16 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) in the range from about 3 Angstroms to about 13 Angstroms.
22. The transistor of claim 16 , wherein the dielectric film exhibits an equivalent oxide thickness (t eq ) of less than 3 Angstroms.
23. A memory comprising:
a number of access transistors in an array, each access transistor having a body region between a source region and a drain region, at least one access transistor including a gate coupled to a dielectric film disposed above the body region, the dielectric film containing a HfSiON layer, the HfSiON layer structured as one or more monolayers, the HfSiON on a transition region between the HfSiON layer and a transistor region on which the dielectric film is disposed such the transition region is a graded material region from the transistor region to the HfSiON layer wherein the HfSiON layer is rich in Hf—O;
a number of word lines coupled to a number of the gates of the number of access transistors;
a number of source lines coupled to a number of the source regions of the number of access transistors; and
a number of bit lines coupled to a number of the drain regions of the number of access transistors.
24. The memory of claim 23 , wherein the gate contacts the dielectric film and the dielectric film contacts the body region.
25. The memory of claim 23 , wherein the gate is a floating gate and the dielectric film is interposed between the floating gate and the body region.
26. The memory of claim 23 , wherein the gate is a control gate and the dielectric film is interposed between the control gate and a floating gate.
27. The memory of claim 23 , wherein the dielectric film has a dielectric constant in the range from about 9 to about 14.
28. The memory of claim 23 , wherein the dielectric film has an equivalent oxide thickness (t eq ) in the range from about 3 Angstroms to about 13 Angstroms.
29. An electronic system comprising:
a processor;
a system bus; and
a memory coupled to the processor by the system bus, the memory including:
a number of access transistors in an array, each access transistor having a body region between a source region and a drain region, at least one access transistor including a gate coupled to a dielectric film disposed above the body region, the dielectric film containing a HfSiON layer, the HfSiON layer structured as one or more monolayers, the HfSiON on a transition region between the HfSiON layer and a transistor region on which the dielectric film is disposed such the transition region is a graded material region from the transistor region to the HfSiON layer wherein the HfSiON layer is rich in Hf—O;
a number of word lines coupled to a number of the gates of the number of access transistors;
a number of source lines coupled to a number of the source region of the number of access transistors;
a number of bit lines coupled to a number of the drain region of the number of access transistors.
30. The electronic system of claim 29 , wherein the dielectric film has a dielectric constant in the range from about 9 to about 14.
31. The electronic system of claim 29 , wherein the film exhibits an equivalent oxide thickness (t eq ) in the range from about 3 Angstroms to about 13 Angstroms.
32. The electronic system of claim 29 , wherein the dielectric layer has a thickness ranging from about 1 nm to 3 nm.
33. The electronic system of claim 29 , wherein the memory is a dynamic random access memory (DRAM).