Programming, erasing, and reading structure for an NVM cell
View Patent ↗A non-volatile memory (NVM) has a silicon germanium (SiGe) drain and a silicon carbon (SiC) source. The source being SiC provides for a stress on the channel that improves N channel mobility. The SiC also has a larger bandgap than the substrate, which is silicon. This results in it being more difficult to generate electron/hole pairs by impact ionization. Thus, it can be advantageous to use the SiC region for the drain during a read. The SiGe is used as the drain for programming and erase. The SiGe, having a smaller bandgap than the silicon substrate results in improved programming by generating electron/hole pairs by impact ionization and improved erasing by generating electron hole/pairs by band-to-band tunneling, both at lower voltage levels.
1. A method of forming a semiconductor device comprising:
providing a substrate of a first conductivity type;
forming a gate stack structure overlying the substrate;
forming a drain region of a second conductivity type adjacent the gate stack structure, the second conductivity type being different from the first conductivity type, and wherein the drain region comprises a material having a smaller bandgap than a bandgap of the substrate; and
forming a source region of a second conductivity type adjacent the gate stack structure and on a side opposite that of the drain region, wherein the source region comprises a material having a larger bandgap than the bandgap of the substrate.
2. The method of claim 1 , wherein the source region comprises a material different from a material of the drain region.
3. The method of claim 1 , wherein forming the source region includes epitaxially growing the larger bandgap material.
4. The method of claim 1 , wherein forming the source region includes implanting to form the larger bandgap material.
5. The method of claim 1 , wherein the source region comprises carbon doped silicon (SiC).
6. The method of claim 1 , wherein the drain region comprises silicon germanium (SiGe).
7. The method of claim 1 , wherein the first conductivity type comprises p-type and the device comprises an NMOS non-volatile memory transistor.
8. The method of claim 1 , wherein the first conductivity type comprises n-type and the device comprises a PMOS non-volatile memory transistor.
9. The method of claim 1 , wherein the gate stack structure includes gate electrode overlying a charge storage layer.
10. The method of claim 1 , wherein the gate stack structure includes a gate electrode overlying a top dielectric layer, the top dielectric layer overlying a charge storage layer, and the charge storage layer overlying a bottom dielectric layer.
11. The method of claim 1 , wherein the device comprises a non-volatile memory transistor, further wherein in response to applying a reading bias to the source region, a content of a charge storage layer of the non-volatile memory can be read with a minimal read disturb, the minimal read disturb corresponding to an occurrence of impact ionization insufficient to adversely affect the content of the charge storage layer.
12. The method of claim 1 , wherein the larger bandgap material of the source region reduces an occurrence of impact ionization in the source region and substantially eliminates any low level charge injection to the gate stack structure that could undesirably affect a charge stored in a charge storage layer of the gate stack structure during a read operation with a biased source and grounded drain.
13. The method of claim 1 , wherein the device comprises a non-volatile memory transistor, further wherein in response to applying a programming bias to the source region, a content of a charge storage layer of the non-volatile memory can be programmed by means of hot carrier injection.
14. A semiconductor device comprising:
a substrate of a first conductivity type;
a gate stack structure overlying the substrate;
a drain region of a second conductivity type adjacent the gate stack structure, the second conductivity type being different from the first conductivity type, and wherein the drain region comprises a material having a smaller bandgap than a bandgap of the substrate; and
a source region of a second conductivity type adjacent the gate stack structure and on a side opposite that of the drain region, wherein the source region comprises a material having a larger bandgap than the bandgap of the substrate.
15. The device of claim 14 , wherein the source region comprises a material different from a material of the drain region.
16. The device of claim 14 , wherein the source region includes an epitaxially grown material.
17. The device of claim 14 , wherein the source region includes a material with an implanted dopant.
18. The device of claim 14 , wherein the source region comprises carbon doped silicon (SiC).
19. The device of claim 14 , wherein the drain region comprises silicon germanium (SiGe).
20. The device of claim 14 , wherein the first conductivity type comprises p-type and further wherein the device comprises an NMOS non-volatile memory transistor.
21. The device of claim 14 , wherein the first conductivity type comprises n-type and further wherein the device comprises a PMOS non-volatile memory transistor.
22. The device of claim 14 , wherein the gate stack structure includes gate electrode overlying a charge storage layer.
23. The device of claim 14 , wherein the gate stack structure includes a gate electrode overlying a top dielectric layer, the top dielectric layer overlying a charge storage layer, and the charge storage layer overlying a bottom dielectric layer.
24. The device of claim 14 , wherein the device comprises a non-volatile memory transistor, further wherein in response to applying a reading bias to the source region, a content of a charge storage layer of the non-volatile memory can be read with a minimal read disturb, the minimal read disturb corresponding to an occurrence of impact ionization insufficient to adversely affect the content of the charge storage layer.
25. The device of claim 14 , wherein the larger bandgap material of the source region reduces an occurrence of impact ionization in the source region and substantially eliminates any low level charge injection to the gate stack structure that could undesirably affect a charge stored in a charge storage layer of the gate stack structure.
26. The device of claim 14 , wherein the device comprises a non-volatile memory transistor, further wherein in response to applying a programming bias to the source region, a content of a charge storage layer of the non-volatile memory can be programmed by means of hot carrier injection.
27. The method of claim 1 , wherein:
the step of forming the source is further characterized by the source comprising carbon doped silicon; and
the step of forming the drain is further characterized by the drain comprising germanium doped silicon.