Method of delay calculation in integrated circuit, and timing analysis system using the same
View Patent ↗In a method of delay calculation of relative timing paths of an integrated circuit, each of the paths contains at least one stage. The method is achieved by calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component; and by carrying out delay calculation of relative timing paths by using the on-chip variation depending on the systematic component and the on-chip variation depending on the random component.
1. A method of delay calculation of relative timing paths of an integrated circuit, said method comprising:
calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component, wherein said on-chip variation depending on said systematic component is based on a distance between two stages on said relative timing paths and a delay time of each of said stages and
said on-chip variation depending on said systematic component is calculated from the following equation set (1);
RTS
n
=
∑
j
=
1
m
TP
2
j
*
VS
(
L
p
1
n
-
p
2
j
)
/
∑
j
=
1
m
TP
2
j
RTS
m
=
∑
i
=
1
n
TP
1
i
*
VS
(
L
p
2
m
-
p
1
i
)
∑
i
=
1
n
TP
1
i
(
1
)
where said relative timing paths contains a first path and a second path, said first path contains n stages, said second path contains m stages, TP 1 n is a delay time of the n-th stage in said first path, TP 2 m is a delay time of the m-th stage in said second path, VS(L p1n-p2m ) is the systematic component at the n-th stage in said first path, L p1n-p2m is a distance between the n-th stage in said first path and the m-th stage in said second path, VS(L p2m-p1n ) is a systematic component of the m-th stage in said second path, L p2m-p1n is a distance between the m-th stage in said second path and the n-th stage in said first path, RTS n is an on-chip variation depending on the systematic component in said first path, and RTS m is an on-chip variation depending on the systematic component in said second path; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.
2. The method according to claim 1 , further comprising: specifying said relative timing paths based on circuit data of said integrated circuit; calculating a distance between stages in said specified paths from layout data; and extracting a stage count of each of said specified paths.
3. A method of delay calculation of relative timing paths of an integrated circuit, said method comprising:
calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component, wherein said on-chip variation depending on said random component is calculated from a calculation depending on a number of said stages wherein said random component is on presumption of an independent normal distribution and
said on-chip variation depending on said random component is calculated from the following equation set (2-1) or (2-2),
RTR n =n·α·TP 1 1 =VR/√{square root over (n)}
RTR m =m·α·TP 2 1 =VR/√{square root over (m)} (2-1)
RTR n =√{square root over (n)}·VR
RTR m =√{square root over (m)}·VR (2-2)
where said relative timing paths contains a first path and a second path, VR is the random component set to each stage in said first path and said second path, RTS n is said on-chip variation depending on said random component in said first path, RTS m is said on-chip variation depending on said random component in said second path, α is a constant coefficient, TP 1 1 is a delay time of a first stage in the first path, TP 2 1 is a delay time of a first stage in the second path, n is the nth stage in said first path and m is the mth stage in said second path; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.
4. The method according to claim 3 , further comprising:
specifying said relative timing paths based on circuit data of said integrated circuit;
calculating a distance between stages in said specified paths from layout data; and
extracting a stage count of each of said specified paths.
5. A method of delay calculation of relative timing paths of an integrated circuit, said method comprising:
calculating an on-chip variation depending on a systematic component and an on-chip variation depending on a random component; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component and by
calculating a variation of delay time of each of said relative timing paths from the following equation set (3), using said on-chip variation depending on said systematic component and said on-chip variation depending on said random component,
TP
1
min
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
-
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
1
max
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
+
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
2
min
(
L
,
m
)
=
∑
i
=
1
m
{
TP
2
j
*
(
1
-
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
TP
2
max
(
L
,
m
)
=
∑
j
=
1
m
{
TP
2
j
*
(
1
+
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
(
3
)
where said relative timing paths contains a first path and a second path, TP 1 max is the maximum delay time of said first path, TP 1 min are the minimum delay time of said first path, TP 2 max is the maximum delay time of said second path, TP 2 min is the minimum delay time of said second path, L is a distance, TP 1 i is the ith delay time of said first path, TP 2 j is the jth delay time of said second path, n is the nth stage in said first path and m is the mth stage in said second path, RTSi is the ith delay time variation depending on a systematic component, RTRi is the ith delay time variation depending on a random component, RTSj is the jth delay time variation depending on a systematic component and RTRj is the jth delay time variation depending on a random component.
6. The method according to claim 5 , further comprising:
specifying said relative timing paths based on circuit data of said integrated circuit;
calculating a distance between stages in said specified paths from layout data; and
extracting a stage count of each of said specified paths.
7. A method of carrying timing analysis of an integrated circuit, comprising:
carrying out delay calculation of relative timing paths;
carrying out setup analysis or hold analysis;
extracting a stage count of each of said specified paths;
calculating an on-chip variation depending on said random component; and
correcting said delay time based on said on-chip variation depending on said random component,
wherein said calculating an on-chip variation depending on said random component comprises:
calculating said on-chip variation depending on said random component from the following equation set (2-1) or (2-2),
RTR n =n·α·TP 1 1 =VR/√{square root over (n)}
RTR m =m·α·TP 2 1 =VR/√{square root over (m)} (2-1)
RTR n =√{square root over (n)}·VR
RTR m =√{square root over (m)}·VR (2-2)
where said relative timing paths contains a first path and a second path, VR is the random component set to each stage in said first path and said second path, RTR n is said on-chip variation depending on said random component in said first path, RTRm is said on-chip variation depending on said random component in said second path, α is a constant coefficient, TP 1 1 is a delay time of a first stage in said first path, TP 2 1 is a delay time of a first stage in said second path, n is the nth stage in said first path and m is the mth stage in said second path.
8. A timing analysis system comprising:
a delay calculation section which calculates a delay time at each of stages in relative timing paths based on circuit data of an integrated circuit;
a path specifying section which extracts and specifies two of said paths of said integrated circuit;
a coordinate data extracting section which determines data of coordinates of said specified paths or a distance between said relative timing paths from layout data;
a stage count extracting section which extracts a number of the stages in each of said specified paths;
a delay time variation calculating section which calculates a systematic component and a random component of an on-chip variation of the delay time of each of said specified paths, wherein said on-chip variation depending on said systematic component is based on a distance between two stages on said relative timing paths and a delay time of each of said stages and
said on-chip variation depending on said systematic component is calculated based on the following equation set (1);
RTS
n
=
∑
j
=
1
m
TP
2
j
*
VS
(
L
p
1
n
-
p
2
j
)
/
∑
j
=
1
m
TP
2
j
RTS
m
=
∑
i
=
1
n
TP
1
i
*
VS
(
L
p
2
m
-
p
1
i
)
∑
i
=
1
n
TP
1
i
(
1
)
where said relative timing paths contains a first path and a second path, said first path contains n stages, said second path contains m stages, TP 1 n is a delay time of the n-th stage in said first path, TP 2 m is a delay time of the m-th stage in said second path, VS(L p1n-p2m ) is the systematic component at the n-th stage in said first path, L p1n-p2m is a distance between the n-th stage in said first path and the m-th stage in said second path, VS(L p2m-p1n ) is a systematic component of the m-th stage in said second path, L p2m-p1n is a distance between the m-th stage in said second path and the n-th stage in said first path, RTS n is an on-chip variation depending on the systematic component in said first path, and RTS m is an on-chip variation depending on the systematic component in said second path; and
a timing analysis section which carries out timing analysis of SETUP and HOLD based on a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.
9. A timing analysis system comprising:
a delay calculation section which calculates a delay time at each of stages in relative timing paths based on circuit data of an integrated circuit;
a path specifying section which extracts and specifies two of said paths of said integrated circuit;
a coordinate data extracting section which determines data of coordinates of said specified paths or a distance between said relative timing paths from layout data;
a stage count extracting section which extracts a number of the stages in each of said specified paths;
a delay time variation calculating section which calculates a systematic component and a random component of an on-chip variation of the delay time of each of said specified paths, wherein said on-chip variation depending on said random component is calculated from a calculation depending on a number of said stages on presumption of an independent normal distribution and
said on-chip variation depending on said random component is calculated from the following equation set (2-1) or (2-2),
RTR n =n·α·TP 1 1 =VR/√{square root over (n)}
RTR m =m·α·TP 2 1 =VR/√{square root over (m)} (2-1)
RTR n =√{square root over (n)}·VR
RTR m =√{square root over (m)}·VR (2-2)
where said relative timing paths contains a first path and a second path, VR is the random component set to each stage in said first path and said second path, RTR n is said on-chip variation depending on said random component in said first path, and RTR m is said on-chip variation depending on said random component in said second path, α is a constant coefficient, TP 1 1 is a delay time of a first stage in said first path, TP 2 1 is a delay time of a first stage in said second path, n is the nth stage in said first path and m is the mth stage in said second path; and
a timing analysis section which carries out timing analysis of SETUP and HOLD based on a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.
10. A timing analysis system comprising:
a delay calculation section which calculates a delay time at each of stages in relative timing paths based on circuit data of an integrated circuit;
a path specifying section which extracts and specifies two of said paths of said integrated circuit;
a coordinate data extracting section which determines data of coordinates of said specified paths or a distance between said relative timing paths from layout data;
a stage count extracting section which extracts a number of the stages in each of said specified paths;
a delay time variation calculating section which calculates a systematic component and a random component of an on-chip variation of the delay time of each of said specified paths and which
calculates a variation of delay time of each of said relative timing paths from the following equation set (3), using said on-chip variation depending on said systematic component and said on-chip variation depending on said random component,
TP
1
min
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
-
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
1
max
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
+
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
2
min
(
L
,
m
)
=
∑
i
=
1
m
{
TP
2
j
*
(
1
-
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
TP
2
max
(
L
,
m
)
=
∑
j
=
1
m
{
TP
2
j
*
(
1
+
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
(
3
)
where said relative timing paths contains a first path and a second path, TP 1 max is the maximum delay time of said first path, TP 1 min are the minimum delay time of said first path, TP 2 max is the maximum delay time of said second path, TP 2 min is the minimum delay time of said second path, L is a distance, TP 1 i is the ith delay time of said first path, TP 2 j is the jth delay time of said second path, n is the nth stage in said first path and m is the mth stage in said second path, RTSi is the ith delay time variation depending on a systematic component, RTRi is the ith delay time variation depending on a random component, RTSj is the jth delay time variation depending on a systematic component and RTRj is the jth delay time variation depending on a random component; and
a timing analysis section which carries out timing analysis of SETUP and HOLD based on a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.
11. A timing analysis system comprising:
a delay calculation section which calculates a delay time at each of stages in relative timing paths based on circuit data of an integrated circuit;
a path specifying section which extracts and specifies two of said paths of said integrated circuit;
a stage count extracting section which extracts a number of the stages in each of said specified paths;
a delay time variation calculating section which calculates a random component of an on-chip variation of the delay time of each of said specified paths; and
a timing analysis section which carries out timing analysis of SETUP and HOLD based on said on-chip variation depending on said random component,
wherein said delay time variation calculating section calculates said on-chip variation depending on said random component from a calculation depending on a number of said stages on presumption of an independent normal distribution, and
wherein said delay time variation calculating section calculates said on-chip variation depending on said random component from the following equation set (2-1) or (2-2),
RTR n =n·α·TP 1 1 =VR/√{square root over (n)}
RTR m =m·α·TP 2 1 =VR/√{square root over (m)} (2-1)
RTR n =√{square root over (n)}·VR
RTR m =√{square root over (m)}·VR (2-2)
where said relative timing paths contains a first path and a second path, VR is the random component set to each stage in said first path and said second path, RTR n is said on-chip variation depending on said random component in said first path, and RTR m is said on-chip variation depending on said random component in said second path, α is a constant coefficient, TP 1 1 is a delay time of a first stage in said first path, TP 2 1 is a delay time of a first stage in said second path, n is the nth stage in said first path and m is the mth stage in said second path.
12. The timing analysis system according to claim 11 , wherein said delay time variation calculating section calculates a variation of delay time of each of said relative timing paths from the following equation set (3), using said on-chip variation depending on said random component,
TP
1
min
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
-
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
1
max
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
+
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
2
min
(
L
,
m
)
=
∑
i
=
1
m
{
TP
2
j
*
(
1
-
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
TP
2
max
(
L
,
m
)
=
∑
j
=
1
m
{
TP
2
j
*
(
1
+
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
(
3
)
where said relative timing paths contains a first path and a second path, TP 1 max is the maximum delay time of said first path, TP 1 min are the minimum delay time of said first path, TP 2 max is the maximum delay time of said second path, TP 2 min is the minimum delay time of said second path, L isa distance, TP 1 i is the ith delay time of said first path, TP 2 j is the jth delay time of said second path, n is the nth stage in said first path and m is the mth stage in said second path, RTSi is the ith delay time variation depending on a systematic component, RTRi is the ith delay time variation depending on a random component, RTSj is the jth delay time variation depending on a systematic component and RTRj is the jth delay time variation depending on a random component.
13. A computer-readable software product for realizing a method of delay calculation of relative timing paths of an integrated circuit, wherein each of said paths contains at least one stage, said method comprising:
calculating an on-chip variation depending on a systematic component;
calculating said on-chip variation depending on a random component; and
carrying out delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component, wherein said on-chip variation depending on said systematic component is based on a distance between two stages on said relative timing paths and a delay time of each of said stages, and carrying out delay calculation of relative timing paths by
calculating said on-chip variation depending on said systematic component from the following equation set (1);
RTS
n
=
∑
j
=
1
m
TP
2
j
*
VS
(
L
p
1
n
-
p
2
j
)
/
∑
j
=
1
m
TP
2
j
RTS
m
=
∑
i
=
1
n
TP
1
i
*
VS
(
L
p
2
m
-
p
1
i
)
/
∑
i
=
1
n
TP
1
i
(
1
)
where said relative timing paths contains a first path and a second path, said first path contains n stages, said second path contains m stages, TP 1 n is a delay time of the n-th stage in said first path, TP 2 m is a delay time of the m-th stage in said second path, VS(L p1n-p2m ) is the systematic component at the n-th stage in said first path, L p1n-p2m is a distance between the n-th stage in said first path and the m-th stage in said second path, VS(L p2m-p1n ) is a systematic component of the m-th stage in said second path, L p2m-p1n is a distance between the m-th stage in said second path and the n-th stage in said first path, RTS n is an on-chip variation depending on the systematic component in said first path, and RTS m is an on-chip variation depending on the systematic component in said second path.
14. The software product according to claim 13 , further comprising:
specifying said relative timing paths based on circuit data of said integrated circuit;
calculating a distance between stages in said specified paths from layout data; and
extracting a stage count of each of said specified paths.
15. A computer-readable software product for realizing a method of delay calculation of relative timing paths of an integrated circuit, wherein each of said paths contains at least one stage, said method comprising:
calculating an on-chip variation depending on a systematic component;
calculating said on-chip variation depending on a random component; and
carrying out delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component, wherein said on-chip variation depending on said random component is from a calculation depending on a number of said stages on presumption of an independent normal distribution, and carrying out delay calculation of relative timing paths by
calculating said on-chip variation depending on said random component from the following equation set (2-1) or (2-2),
RTR n =n·α·TP 1 1 =VR/√{square root over (n)}
RTR m =m·α·TP 2 1 =VR/√{square root over (m)} (2-1)
RTR n =√{square root over (n)}·VR
RTR m =√{square root over (m)}·VR (2-2)
where said relative timing paths contains a first path and a second path, VR is the random component set to each stage in said first path and said second path, RTS n is said on-chip variation depending on said random component in said first path, and RTS m is said on-chip variation depending on said random component in said second path, α is a constant coefficient, TP 1 1 is a delay time of a first stage in said first path, TP 2 1 is a delay time of a first stage in said second path, n is the nth stage in said first path and m is the mth stage in said second path.
16. The software product according to claim 15 , further comprising:
specifying said relative timing paths based on circuit data of said integrated circuit;
calculating a distance between stages in said specified paths from layout data; and
extracting a stage count of each of said specified paths.
17. A computer-readable software product for realizing a method of delay calculation of relative timing paths of an integrated circuit, wherein each of said paths contains at least one stage, said method comprising:
calculating an on-chip variation depending on a systematic component;
calculating said on-chip variation depending on a random component; and
carrying out delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component and by
calculating a variation of delay time of each of said relative timing paths from the following equation set (3), using said on-chip variation depending on said systematic component and said on-chip variation depending on said random component,
TP
1
min
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
-
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
1
max
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
+
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
2
min
(
L
,
m
)
=
∑
i
=
1
m
{
TP
2
j
*
(
1
-
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
TP
2
max
(
L
,
m
)
=
∑
j
=
1
m
{
TP
2
j
*
(
1
+
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
(
3
)
where said relative timing paths contains a first path and a second path, TP 1 max is the maximum delay time of said first path, TP 1 min are the minimum delay time of said first path, TP 2 max is the maximum delay time of said second path, TP 2 min is the minimum delay time of said second path L is a distance, TP 1 i is the ith delay time of said first path, TP 2 j is the jth delay time of said second path, n is the nth stage in said first path and m is the mth stage in said second path, RTSi is the ith delay time variation depending on a systematic component, RTRi is the ith delay time variation depending on a random component, RTSj is the jth delay time variation depending on a systematic component and RTRj is the jth delay time variation depending on a random component.
18. The software product according to claim 17 , further comprising:
specifying said relative timing paths based on circuit data of said integrated circuit;
calculating a distance between stages in said specified paths from layout data; and
extracting a stage count of each of said specified paths.
19. A method of designing an integrated circuit, said method comprising:
preparing a circuit design data of said integrated circuit;
preparing a layout design data of said integrated circuit;
calculating an on-chip variation depending on a systematic component based on said layout design data, wherein said on-chip variation depending on said systematic component is based on a distance between two stages on said relative timing paths and a delay time of each of said stages and said on-chip variation depending on said systematic component is calculated from the following equation set (1);
RTS
n
=
∑
j
=
1
m
TP
2
j
*
VS
(
L
p
1
n
-
p
2
j
)
/
∑
j
=
1
m
TP
2
j
RTS
m
=
∑
i
=
1
n
TP
1
i
*
VS
(
L
p
2
m
-
p
1
i
)
/
∑
i
=
1
n
TP
1
i
(
1
)
where said relative timing paths contains a first path and a second path, said first path contains n stages, said second path contains m stages, TP 1 n is a delay time of the n-th stage in said first path, TP 2 m is a delay time of the m-th stage in said second path, VS(L p1n-p2m ) is the systematic component at the n-th stage in said first path, L p1n-p2m is a distance between the n-th stage in said first path and the m-th stage in said second path, VS(L p2m-p1n ) is a systematic component of the m-th stage in said second path, L p2m-p1n is a distance between the m-th stage in said second path and the n-th stage in said first path, RTS n is an on-chip variation depending on the systematic component in said first path, and RTS m is an on-chip variation depending on the systematic component in said second path;
calculating an on-chip variation depending on a random component based on said circuit design data; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.
20. A method of manufacturing an integrated circuit, said method comprising:
preparing a circuit design data and layout design data of said integrated circuit;
executing a delay calculation of relative timing paths of said integrated circuit;
manufacturing said integrated circuit based on said delay calculation of relative timing paths,
wherein said delay calculation of relative timing paths comprises;
calculating an on-chip variation depending on a systematic component based on said layout design data, wherein said on-chip variation depending on said systematic component is based on a distance between two stages on said relative timing paths and a delay time of each of said stages and said on-chip variation depending on said systematic component is calculated from the following equation set (1);
RTS
n
=
∑
j
=
1
m
TP
2
j
*
VS
(
L
p
1
n
-
p
2
j
)
/
∑
j
=
1
m
TP
2
j
RTS
m
=
∑
i
=
1
n
TP
1
i
*
VS
(
L
p
2
m
-
p
1
i
)
/
∑
i
=
1
n
TP
1
i
(
1
)
where said relative timing paths contains a first path and a second path, said first path contains n stages, said second path contains m stages, TP 1 n is a delay time of the n-th stage in said first path, TP 2 m is a delay time of the m-th stage in said second path, VS(L p1n-p2m ) is the systematic component at the n-th stage in said first path, L p1n-p2m is a distance between the n-th stage in said first path and the m-th stage in said second path, VS(L p2m-p1n ) is a systematic component of the m-th stage in said second path, L p2m-p1n is a distance between the m-th stage in said second path and the n-th stage in said first path, RTS n is an on-chip variation depending on the systematic component in said first path, and RTS m is an on-chip variation depending on the systematic component in said second path; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and an on-chip variation depending on a random component.
21. A method of designing an integrated circuit, said method comprising:
preparing a circuit design data of said integrated circuit;
preparing a layout design data of said integrated circuit;
calculating an on-chip variation depending on a systematic component based on said layout design data;
calculating an on-chip variation depending on a random component based on said circuit design data, wherein said on-chip variation depending on said random component is calculated from a calculation depending on a number of said stages wherein said random component is on presumption of an independent normal distribution and said on-chip variation depending on said random component is calculated from the following equation set (2-1) or (2-2),
RTR n =n·α·TP 1 1 =VR/√{square root over (n)}
RTR m =m·α·TP 2 1 =VR/√{square root over (m)} (2-1)
RTR n =√{square root over (n)}·VR
RTR m =√{square root over (m)}·VR (2-2)
where said relative timing paths contains a first path and a second path, VR is the random component set to each stage in said first path and said second path, RTS n is said on-chip variation depending on said random component in said first path, RTS m is said on-chip variation depending on said random component in said second path, α is a constant coefficient, TP 1 1 is a delay time of a first stage in the first path, TP 2 1 is a delay time of a first stage in the second path, n is the nth stage in said first path and m is the mth stage in said second path; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.
22. A method of designing an integrated circuit, said method comprising:
preparing a circuit design data of said integrated circuit;
preparing a layout design data of said integrated circuit;
calculating an on-chip variation depending on a systematic component based on said layout design data;
calculating an on-chip variation depending on a random component based on said circuit design data; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component and by calculating a variation of delay time of each of said relative timing paths from the following equation set (3), using said on-chip variation depending on said systematic component and said on-chip variation depending on said random component,
TP
1
min
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
-
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
1
max
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
+
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
2
min
(
L
,
m
)
=
∑
i
=
1
m
{
TP
2
j
*
(
1
-
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
TP
2
max
(
L
,
m
)
=
∑
j
=
1
m
{
TP
2
j
*
(
1
+
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
(
3
)
where said relative timing paths contains a first path and a second path, TP 1 max is the maximum delay time of said first path, TP 1 min are the minimum delay time of said first path, TP 2 max is the maximum delay time of said second path, TP 2 min is the minimum delay time of said second path, L is a distance, TP 1 i is the ith delay time of said first path, TP 2 j is the jth delay time of said second path, n is the nth stage in said first path and m is the mth stage in said second path, RTSi is the ith delay time variation depending on a systematic component, RTRi is the ith delay time variation depending on a random component, RTSj is the jth delay time variation depending on a systematic component and RTRj is the jth delay time variation depending on a random component.
23. A method of manufacturing an integrated circuit, said method comprising:
preparing a circuit design data and layout design data of said integrated circuit;
executing a delay calculation of relative timing paths of said integrated circuit;
manufacturing said integrated circuit based on said delay calculation of relative timing paths,
wherein said delay calculation of relative timing paths comprises;
calculating an on-chip variation depending on a systematic component based on said layout design data;
calculating an on-chip variation depending on a random component based on said circuit design data, wherein said on-chip variation depending on said random component is calculated from a calculation depending on a number of said stages wherein said random component is on presumption of an independent normal distribution and said on-chip variation depending on said random component is calculated from the following equation set (2-1) or (2-2),
RTR n =n·α·TP 1 1 =VR/√{square root over (n)}
RTR m =m·α·TP 2 1 =VR/√{square root over (m)} (2-1)
RTR n =√{square root over (n)}·VR
RTR m =√{square root over (m)}·VR (2-2)
where said relative timing paths contains a first path and a second path, VR is the random component set to each stage in said first path and said second path, RTS n is said on-chip variation depending on said random component in said first path, RTS m is said on-chip variation depending on said random component in said second path, α is a constant coefficient, TP 1 1 is a delay time of a first stage in the first path, TP 2 1 is a delay time of a first stage in the second path, n is the nth stage in said first path and m is the mth stage in said second path; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component.
24. A method of manufacturing an integrated circuit, said method comprising:
preparing a circuit design data and layout design data of said integrated circuit;
executing a delay calculation of relative timing paths of said integrated circuit;
manufacturing said integrated circuit based on said delay calculation of relative timing paths,
wherein said delay calculation of relative timing paths comprises;
calculating an on-chip variation depending on a systematic component based on said layout design data;
calculating an on-chip variation depending on a random component based on said circuit design data; and
carrying out a delay calculation of relative timing paths by using a square root sum of squares of said on-chip variation depending on said systematic component and said on-chip variation depending on said random component and by calculating a variation of delay time of each of said relative timing paths from the following equation set (3), using said on-chip variation depending on said systematic component and said on-chip variation depending on said random component,
TP
1
min
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
-
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
1
max
(
L
,
n
)
=
∑
i
=
1
n
{
TP
1
i
*
(
1
+
(
RTS
i
)
2
+
(
RTR
i
)
2
)
}
TP
2
min
(
L
,
m
)
=
∑
i
=
1
m
{
TP
2
j
*
(
1
-
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
TP
2
max
(
L
,
m
)
=
∑
j
=
1
m
{
TP
2
j
*
(
1
+
(
RTS
j
)
2
+
(
RTR
j
)
2
)
}
(
3
)
where said relative timing paths contains a first path and a second path, TP 1 max is the maximum delay time of said first path, TP 1 min are the minimum delay time of said first path, TP 2 max is the maximum delay time of said second path, TP 2 min is the minimum delay time of said second path, L is a distance, TP 1 i is the ith delay time of said first path, TP 2 j is the jth delay time of said second path, n is the nth stage in said first path and m is the mth stage in said second path, RTSi is the ith delay time variation depending on a systematic component, RTRI is the ith delay time variation depending on a random component, RTSj is the jth delay time variation depending on a systematic component and RTRj is the jth delay time variation depending on a random component.