Embedded DRAM cache memory and method having reduced latency

1. A memory system for use with a processor based system having a processor and a system memory, the memory system comprising:

a system memory controller structured to control the system memory of the processor based system;

a processor interface coupled to the system memory controller, the processor interface structured to transmit information between the processor and the system memory; and

a cache memory coupled to the system memory controller and the processor interface, the cache memory being operable to receive a request for access to the cache memory, and, in response thereto, to initiate a read operation in the cache memory before determining whether the access to the cache memory will result in a cache hit, the cache memory being operable to couple read data from the cache memory to the processor in response to determining that the access will result in a cache hit.

2. The memory system of claim 1 wherein the cache memory is further operable to apply to the system memory controller a request for access to the system memory responsive to receiving the request for access to the cache memory and before the cache memory has determined whether the access to the cache memory will result in a cache hit, the cache memory being further operable to couple data accessed from the system memory to the processor responsive to the cache memory determining that the access to the cache memory will not result in a cache hit.

3. The memory system of claim 1 wherein the cache memory is further operable in response to determining that the access will not result in a cache hit to apply a request to the system memory controller for access to the system memory.

4. The memory system of claim 3 wherein the cache memory is further operable to receive data from the system memory responsive to the request for access to the system memory and to write the data received from the system memory to the cache memory.

5. The memory system of claim 1 wherein the system memory controller, processor interface and cache memory are fabricated as an integrated circuit on a common substrate.

6. A memory system for use with a processor based system having a processor and a system memory, the memory system comprising:

a system memory controller structured to control the system memory of the processor based system;

a processor interface coupled to the system memory controller, the processor interface structured to transmit information between the processor and the system memory; and

a cache memory coupled to the system memory controller and the processor interface, the cache memory being operable to receive a request for access to the cache memory, and, in response thereto to initiate an access to the cache memory and an access to the system memory, the cache memory being operable to initiate an access to the system memory before the cache memory has determined whether the access to the cache memory will result in a cache hit, the cache memory being further operable to couple data accessed from the system memory to the processor responsive to the cache memory determining that the access to the cache memory will not result in a cache hit.

7. The memory system of claim 6 wherein the cache memory is operable to initiate a read operation in the cache memory before the cache memory has determined whether the access to the cache memory will result in a cache hit.

8. The memory system of claim 7 wherein the cache memory is further operable to couple read data from the cache memory to the processor in response to determining that the access will result in a cache hit.

9. The memory system of claim 6 wherein, in response to determining that the access will not result in a cache hit, the cache memory is operable to receive data from the system memory responsive to the request for access to the system memory and to write the data received from the system memory to the cache memory.

10. The memory system of claim 6 wherein the system memory controller, processor interface and cache memory are fabricated as an integrated circuit on a common substrate.

11. A computer system comprising:

a processor;

a system memory;

a system controller coupled to the processor and to the system memory, the system controller comprising:

a memory controller coupled to the system memory, the memory controller being structured to control the system memory;

a processor interface coupled to the processor, the processor interface structured to transmit information between the processor and the memory controller; and

a cache memory coupled to the memory controller, the cache memory being operable to receive a request for access to the cache memory, and, in response thereto, to initiate a read operation in the cache memory before determining whether the access to the cache memory will result in a cache hit, the cache memory being operable to couple read data from the cache memory to the processor in response to determining that the access will result in a cache hit.

12. The computer system of claim 11 wherein the cache memory is further operable to apply to the memory controller a request for access to the system memory responsive to receiving the request for access to the cache memory and before the cache memory has determined whether the access to the cache memory will result in a cache hit, the cache memory being further operable to couple data accessed from the system memory to the processor responsive to the cache memory determining that the access to the cache memory will not result in a cache hit.

13. The computer system of claim 11 wherein the cache memory is further operable in response to determining that the access will not result in a cache hit to apply a request to the memory controller for access to the system memory.

14. The computer system of claim 13 wherein the cache memory is further operable to receive data from the system memory responsive to the request for access to the system memory and to write the data received from the system memory to the cache memory.

15. The computer system of claim 13 wherein the memory controller, processor interface and cache memory are fabricated as an integrated circuit on a common substrate.

16. A computer system comprising:

a processor;

a system memory;

a system controller coupled to the processor and to the system memory, the system controller comprising:

a memory controller coupled to the system memory, the system memory controller being structured to control the system memory;

a processor interface coupled to the processor, the processor interface structured to transmit information between the processor and the system controller; and

a cache memory coupled to the memory controller and the processor interface, the cache memory being operable to receive a request for access to the cache memory, and, in response thereto to initiate an access to the cache memory and an access to the system memory, the cache memory being operable to initiate an access to the system memory before the cache memory has determined whether the access to the cache memory will result in a cache hit, the cache memory being further operable to couple data accessed from the system memory to the processor responsive to the cache memory determining that the access to the cache memory will not result in a cache hit.

17. The computer system of claim 16 wherein the cache memory is operable to initiate a read operation in the cache memory before the cache memory has determined whether the access to the cache memory will result in a cache hit.

18. The computer system of claim 14 wherein the cache memory is further operable to couple read data from the cache memory to the processor in response to determining that the access will result in a cache hit.

19. The computer system of claim 16 wherein, in response to determining that the access will not result in a cache hit, the cache memory is operable to receive data from the system memory responsive to the request for access to the system memory and to write the data received from the system memory to the cache memory.

20. The computer system of claim 16 wherein the system controller comprises an integrated circuit in which the memory controller, processor interface and cache memory are fabricated in a common integrated circuit.

21. In a processor-based system having a memory requester, a system memory, and a cache memory, a method of accessing data or instructions stored in the system memory and possibly also in the cache memory, the method comprising:

generating at the memory requester a request for access to the data or instructions;

coupling the request for access to the data or instructions to the cache memory;

receiving at the cache memory the request for access to the data or instructions; and

initiating an access to the system memory for the data or instructions before determining whether the access to the cache memory will result in a cache hit or a cache miss.

22. The method of claim 21 , further comprising coupling data or instructions from the cache memory to the memory requestor in response to determining that the access to the cache memory will result in a cache hit.

23. The method of claim 21 , further comprising coupling data or instructions from the system memory to the memory requestor in response to determining that the access to the cache memory will result in a cache miss.

24. The method of claim 23 , further comprising writing the data or instructions received from the system memory to the cache memory.

25. The method of claim 21 , further comprising applying to the system memory a request for access to the system memory responsive to receiving the request for access to the data or instructions.

26. The method of claim 25 wherein the act of applying a request for access to the system memory to the system memory comprises applying the request for access to the system memory to the system memory before determining whether the access to the cache memory will result in a cache hit or a cache miss.

27. In a computer system having a memory requester, a system memory, and a cache memory, a method of accessing data or instructions stored in the system memory and possibly also in the cache memory, the method comprising:

generating at the memory requester a request for access to the data or instructions;

coupling the request for access to the data or instructions to the cache memory;

receiving at the cache memory the request for access to the data or instructions;

initiating an access to the cache memory responsive to receiving the request for access to the data or instructions; and

applying to the system memory a request for access to the system memory responsive to receiving the request for access to the data or instructions, the request for access to the system memory being applied to the system memory before determining whether the access to the cache memory will result in a cache hit or a cache miss.

28. The method of claim 27 , further comprising coupling data or instructions from the cache memory to the memory requestor in response to determining that the access to the cache memory will result in a cache hit.

29. The method of claim 27 , further comprising coupling data or instructions from the system memory to the memory requestor in response to determining that the access to the cache memory will result in a cache miss.

30. The method of claim 29 , further comprising writing the data or instructions received from the system memory to the cache memory.

31. The method of claim 27 wherein the act of initiating an access to the cache memory responsive to receiving the request for access to the data or instructions comprises initiating the access to the cache before determining whether the access to the cache memory will result in a cache hit or a cache miss.

32. In a computer system having a memory requester, a system memory, and a cache memory, a method of accessing data or instructions stored in the system memory and possibly also in the cache memory, the method comprising:

generating at the memory requester a request for access to the data or instructions;

coupling the request for access to the data or instructions to the cache memory;

receiving at the cache memory the request for access to the data or instructions; and

initiating a read operation in the cache memory responsive to receiving the request for access to the data or instructions, the read operation being initiated before determining whether the access to the cache memory will result in a cache hit or a cache miss.

33. The method of claim 32 , further comprising coupling data or instructions from the cache memory to the memory requestor in response to determining that the access to the cache memory will result in a cache hit.

34. The method of claim 32 , further comprising coupling data or instructions from the system memory to the memory requestor in response to determining that the access to the cache memory will result in a cache miss.

35. The method of claim 34 , further comprising writing the data or instructions received from the system memory to the cache memory.

36. The method of claim 32 , further comprising applying to the system memory a request for access to the system memory responsive to receiving the request for access to the data or instructions, the request for access to the system memory being applied to the system memory before determining whether the access to the cache memory will result in a cache hit or a cache miss.