Apparatus and methods for the automated creation of distributed configuration storage

1. A method of providing configuration storage in a device, said method comprising:

placing subsets of said configuration storage in physically non-contiguous areas on said device corresponding to interfaces of said device that each use configuration storage, wherein each said interface comprises:

a processor interface comprising a first subset of said subsets of configuration storage,

a memory interface comprising a second subset of said subsets of configuration storage, and

a system bus interface comprising a third subset of said subsets of configuration storage;

receiving information in a tabular format regarding at least one register bit in said configuration storage for each interface of said device that uses configuration storage; and

scripting said tabular format into a hardware description language (HDL) code containing hardware information for said register bit.

2. The method of claim 1 wherein said receiving information comprises receiving information in a tabular format to configure said register bit to be one of a read only register, a read and write register, a write one to clear register, a write set once and readable register, a read only status register, and a read and write status register.

3. The method of claim 1 further comprising setting said register bit to indicate one of a read only register, a read and write register, a write one to clear register, a write set once and readable register, a read only status register, and a read and write status register.

4. The method of claim 1 further comprising receiving information for register bits for each interface that uses configuration storage in different tabular formats.

5. The method of claim 1 wherein said scripting comprises scripting said tabular format into HDL code using a Visual Basic script tool.

6. The method of claim 1 wherein said scripting comprises scripting said tabular format into HDL code using a Perl script tool.

7. The method of claim 1 wherein said HDL code is Very High Speed Integrated Circuit HDL code.

8. The method of claim 1 wherein said HDL code is Verilog code.

9. The method of claim 1 further comprising automatically creating test code to generate test patterns for simulating said configuration storage in a system environment.

10. A method for providing configuration storage in a device, said method comprising:

receiving information in a tabular format regarding at least one register bit in said configuration storage for a host interface, a memory interface, and a system bus interface of said device where each interface uses a respective subset of configuration storage, and where none of said subsets of said configuration storage is physically contiguous with any other of said subsets of said configuration storage;

scripting said tabular format into a hardware description language (HDL) code containing hardware information for said register bit; and

combining said HDL code with an HDL design file, wherein said HDL design file comprises HDL code for predefined sections of the device, and further wherein said combining eliminates unconnected inputs and outputs in said device.

11. The method of claim 10 wherein said receiving information comprises receiving information in a tabular format to configure said register bit to be one of a read only register, a read and write register, a write one to clear register, a write set once and readable register, a read only status register, and a read and write status register.

12. The method of claim 10 further comprising setting said register bit to indicate one of a read only register, a read and write register, a write one to clear register, a write set once and readable register, a read only status register, and a read and write status register.

13. The method of claim 10 further comprising receiving information for register bits for each interface that uses configuration storage in different tabular formats.

14. The method of claim 10 further comprising automatically creating test code to generate test patterns for simulating said configuration storage in a system environment.

15. The method of claim 10 further comprising automatically logically tying unused register bits in said configuration storage to a binary value.

16. A method for providing configuration storage in a device, said method comprising:

receiving information in a tabular format regarding at least one register bit in said configuration storage for a host interface, a memory interface, and a system bus interface of said device where each interface uses a respective subset of configuration storage, and where none of said subsets of said configuration storage is physically contiguous with any other of said subsets of said configuration storage;

integrating said tabular format into a chip specification for each interface of said device that uses said configuration storage;

scripting said chip specification into a hardware description language (HDL) code containing hardware information for said chip specification; and

combining said HDL code with an HDL design file, wherein said HDL design file comprises HDL code for predefined sections of the device, and further wherein said combining eliminates unconnected inputs and outputs in said device

17. The method of claim 16 further comprising combining said HDL code with at least one HDL design file, wherein said HDL design file is a template comprising HDL code for at least one section of said device that does not change between each design section.

18. The method of claim 17 further comprising releasing and storing said combined HDL code and HDL design file in a second HDL design file.

19. The method of claim 18 further comprising:

importing said second HDL design file into a place-and-route tool;

generating a netlist that describes electrical connectivity data of said device based on said second HDL design file; and

fabricating said device on a chip based on the netlist.

20. The method of claim 19 wherein said chip comprises one of a programmable logic device, an application-specific integrated circuit, and a field-programmable gate array.

21. Data processing apparatus comprising:

means for receiving information in a tabular format regarding at least one register bit in said configuration storage for a host interface, a memory interface, and a system bus interface of said device where each interface uses a respective subset of configuration storage, and where none of said subsets of said configuration storage is physically contiguous with any other of said subsets of said configuration storage;

means for scripting said tabular format into a hardware description language (HDL) code containing hardware information for said register bit; and

means for combining said HDL code with an HDL design file, wherein said HDL design file comprises HDL code for predefined sections of the device, and further wherein said combining eliminates unconnected inputs and outputs in said device

22. Data processing apparatus comprising:

means for receiving information in a tabular format regarding at least one register bit in said configuration storage for a host interface, a memory interface, and a system bus interface of said device where each interface uses a respective subset of configuration storage, and where none of said subsets of said configuration storage is physically contiguous with any other of said subsets of said configuration storage;

means for integrating said tabular format into a chip specification for each interface of said device that uses said configuration storage;

means for scripting said chip specification into a hardware description language (HDL) code containing hardware information for said chip specification; and

combining said HDL code with an HDL design file, wherein said HDL design file comprises HDL code for predefined sections of the device, and further wherein said combining eliminates unconnected inputs and outputs in said device.