Method and program for verifying logic circuit having asynchronous interface
A method of verifying functionality of a logic circuit containing asynchronous interfaces with sufficient accuracy and efficiency. When an RTL code is given, the asynchronous point extraction program extracts therefrom all asynchronous points and creates an asynchronous point list that enumerates them. A control task inserter modifies the RTL code with additional control tasks, as well as producing a control card for a clock & delay controller. The modified RTL code is then directed to a logic simulator. Control tasks inserted in the RTL code permit the simulator to cooperate with the clock & delay controller, so that modulated clocks and delayed signals will act on the RTL model during a logic simulation. A wide range of possible delay situations are produced in the logic simulation phase prior to logic synthesis, which enables accurate and efficient verification of a logic circuit containing asynchronous interfaces.
1 . A method of verifying behavior of a logic circuit having an asynchronous interface, comprising the steps of:
extracting an asynchronous point from a logic circuit defined at a register transfer level; and
verifying functionality of the logic circuit through simulation, taking into account a delay that could occur at the extracted asynchronous point.
2 . The method according to claim 1 , wherein the delay is: produced by modulating a clock signal in the logic circuit according to given parameters.
3 . The method according to claim 1 , wherein the delay is produced by inserting a signal delay to the logic circuit according to given parameters.
4 . The method according to claim 2 , wherein said modulating of the clock signal comprises the substeps of:
inserting a clock modulation task to a specified clock path in the logic circuit; and
giving a modulated clock to the clock modulating task inserted.
5 . The method according to claim 2 , wherein the modulation is applied to each cycle of the clock signal to be modulated.
6 . The method according to claim 3 , wherein said inserting of the signal delay comprises the substeps of:
inserting a delay control task to the logic circuit; and
giving the signal delay to the delay control task inserted.
7 . The method according to claim 3 , further comprising the steps of:
recording a delay value used at each simulation session; and
executing again a past simulation session with a particular delay value when said particular delay value is specified.
8 . A program product stored in a computer-readable storage medium for verifying behavior of a logic circuit having an asynchronous interface, the program product causing a computer system to function as an apparatus comprising:
an asynchronous point extractor that extracts an asynchronous point in a logic circuit defined at a register transfer level; and
a verifier that verifies functionality of the logic circuit through simulation, taking into account a delay that could occur at the asynchronous point extracted by said asynchronous point extractor.
9 . The program product according to claim 8 , wherein said verifier produces the delay by modulating a clock signal in the logic circuit according to given parameters.
10 . The program product according to claim 8 , wherein said verifier produces the delay by inserting a signal delay to the logic circuit according to given parameters.
11 . The program product according to claim 9 , wherein said verifier inserts a clock modulation task to a specified clock path in the logic circuit and gives a modulated clock to the clock modulating task inserted.
12 . The program product according to claim 9 , wherein said verifier applies the modulation to each cycle of the clock signal to be modulated.
13 . The program product according to claim 10 , wherein said verifier inserts a delay control task to the logic circuit and gives the signal delay to the delay control task inserted.
14 . The program product according to claim 10 , wherein said verifier records a delay value used at each simulation session and executes again a past simulation session with a particular delay value when said particular delay value is specified.
15 . A program product stored in a computer-readable storage medium for verifying behavior of a logic circuit having an asynchronous interface, the program product causing a computer system to function as an apparatus comprising:
a control task inserter that inserts a control task to an asynchronous point in a logic circuit defined at a register transfer level; and
a delay controller that uses the control task to produce a delay in the logic circuit during a simulation thereof.
16 . The program product according to claim 15 , wherein said delay controller produces the delay by giving a modulated clock to the control task in the logic circuit according to given parameters.
17 . The program product according to claim 15 , wherein said delay controller produces the delay by giving a signal delay to the control task in the logic circuit according to given parameters.
18 . A system for verifying behavior of a logic circuit having an asynchronous interface, comprising:
an asynchronous point extractor that extracts an asynchronous point in a logic circuit defined at a register transfer level; and
a verifier that verifies functionality of the logic circuit through simulation, taking into account a delay that could occur at the asynchronous point extracted by said asynchronous point extractor.
19 . The system according to claim 18 , wherein said verifier produces the delay by modulating a clock signal in the logic circuit according to given parameters.
20 . The system according to claim 18 , wherein said verifier produces the delay by inserting a signal delay to the logic circuit according to given parameters.
21 . The system according to claim 19 , wherein said verifier inserts a clock modulation task to a specified clock path in the logic circuit and gives a modulated clock to the clock modulating task inserted.
22 . The system according to claim 19 , wherein said verifier applies the modulation to each cycle of the clock signal to be modulated.
23 . The system according to claim 20 , wherein said verifier inserts a delay control task to the logic circuit and gives the signal delay to the delay control task inserted.
24 . The system according, to claim 20 , wherein said verifier records a delay value used at each simulation session and executes again a past simulation session with a particular delay value when said particular delay value is specified.
25 . A system for verifying behavior of a logic circuit having an asynchronous interface, comprising:
a control task inserter that inserts a control task to an asynchronous point in a logic circuit defined at a register transfer level; and
a delay controller that uses the control task to produce a delay in the logic circuit during a simulation thereof.
26 . The system according to claim 25 , wherein said delay controller produces the delay by giving a modulated clock to the control task in the logic circuit according to given parameters.
27 . The system according to claim 25 , wherein said verifier produces the delay by giving a signal delay to the control task in the logic circuit according to given parameters.