Vertical JFET as used for selective component in a memory array
Systems and methods are disclosed that facilitate providing a selective functionality to a polymer memory cell in a memory array while increasing device density in the memory cell array. A vertical JFET is described to which voltages can be selectively applied to control internal current flow there through, which in turn can be employed to manipulate the state of a polymer memory cell coupled to the vertical JFET. By mitigating gaps between gates, or wordlines, and drains of the vertical JFETs, feature size can be reduced to permit increased device density. Furthermore, vertical JFETs in the array can be coupled to gates on only two opposite sides, permitting the JFETs to be arranged without gate crossbars between them, further increasing device density. In this manner, the present invention provides switching characteristics to a memory cell and overcomes problematic bulkiness associated with conventional MOS devices.
1 . A semiconductor device that facilitates increasing device density in a memory cell array, comprising:
a vertical JFET that provides selectivity in the semiconductor device; and
a polymer memory cell that is controlled in part by internal current flow through the vertical JFET.
2 . The semiconductor device of claim 1 , the vertical JFET comprises a drain, a source, and a gate that is vertically positioned to surround the drain.
3 . The semiconductor device of claim 2 , the gate and drain are physically positioned to minimize any space there between to reduce critical dimension of the vertical JFET.
4 . The semiconductor device of claim 1 , the vertical JFET comprises a source, a drain, and a gate that extends along two opposite sides of the drain to permit positioning of a plurality of vertical JFETs in closer proximity to each other.
5 . The semiconductor device of claim 4 , the gate is a wordline.
6 . The semiconductor device of claim 5 , the wordline and drain abut one another to mitigate empty space there between and to reduce feature size of the semiconductor device.
7 . The semiconductor device of claim 6 , further comprising an oxide layer formed over the vertical JFET that has a contact hole aligned with the drain of the vertical JFET.
8 . The semiconductor device of claim 7 , further comprising a metal contact inserted into the contact hole.
9 . The semiconductor device of claim 8 , further comprising a passive layer formed over the metal contact and beneath the polymer memory cell, and operatively coupled to the drain of the vertical JFET by the metal contact.
10 . The semiconductor device of claim 9 , further comprising a bitline positioned over the polymer memory cell and arranged in a non-parallel orientation to the wordline.
11 . A memory cell array comprising a plurality of the semiconductor device of claim 10 .
12 . The memory cell array of claim 10 , at least two of the plurality of semiconductor devices are connected by a single bitline.
13 . The memory cell array of claim 12 , at least two of the plurality of semiconductor devices are connected by a single wordline.
14 . A method for providing an array of semiconductor devices, comprising:
forming a plurality of vertical JFETs on a substrate;
constructing a plurality of polymer memory cells that are operably coupled to the vertical JFETs, and which are selectively controlled by current flow through the vertical JFETs; and
electrically coupling the plurality of memory cells to at least one bitline.
15 . The method of claim 14 , forming a vertical JFET comprises:
forming at least one wordline on a substrate;
forming a drain that is bordered on at least two sides by the wordline;
depositing an oxide layer over the at least one wordline;
forming a contact hole in the oxide layer aligned with the at least one wordline; and
doping the drain through the contact hole.
16 . The method of claim 15 , further comprising doping the substrate to provide a source for the vertical JFETs.
17 . The method of claim 16 , further comprising minimizing a gap between the wordline and the drain to reduce the feature size of the vertical JFET.
18 . The method of claim 17 , further comprising inserting a metal contact into the contact hole.
19 . The method of claim 18 , constructing a polymer memory cell comprises:
depositing a passive layer over the contact;
forming a polymer memory layer over the passive layer.
20 . The method of claim 19 , further comprising orienting bitlines substantially perpendicular to wordlines such that wordline and a bitline have a single intersection at which a semiconductor device is positioned in the array of semiconductor devices.
21 . A system that facilitates providing a selective element to a memory cell in an array of memory cells, comprising:
means for constructing a vertical JFET that controls a state of a memory cell;
means for operatively coupling the vertical JFET to the memory cell; and
means for electrically connecting a plurality of memory cells coupled to vertical JFETs in an array.
22 . The system of claim 21 , further comprising means for selectively applying at least one voltage to the means for electrically connecting a plurality of memory cells coupled to vertical JFETs to permit control of the state of at least one memory cell in the array.