Semiconductor device
View Patent ↗A semiconductor device is disclosed in which a barrier layer is deposited on the sides of the mesa. The barrier layer may comprise a semiconductor material. The barrier layer reduces diffusion of dopants into the active region of the device.
1. A semiconductor device comprising:
a substrate;
a first cladding layer formed on the substrate;
a multiple quantum well structure formed between the first cladding layer and a second cladding layer, the first cladding layer, the multiple quantum well structure and the second cladding layer being processed to form a mesa;
a barrier layer deposited on the sides of the mesa, wherein the barrier layer comprises semiconductor material and an n-type dopant selected from the group consisting of sulfur, silicon, selenium, copper and tin; and
overgrowth layers deposited on the sides of the mesa over the barrier layer in the order: (i) n-type semiconductor; (ii) p-type semiconductor; (iii) intrinsic semiconductor; and (iv) n-type semiconductor.
2. A semiconductor device according to claim 1 , wherein the barrier layer comprises indium phosphide.
3. A semiconductor device comprising:
a first cladding layer formed on a substrate;
a multiple quantum well structure formed between the first cladding layer and a second cladding layer, the first cladding layer, the multiple quantum well structure and the second cladding layer being processed to form a mesa;
a barrier layer deposited on the sides of the mesa, wherein the barrier layer comprises semiconductor material and an n-type dopant selected from the group consisting of sulfur, silicon, selenium, copper and tin; and
overgrowth layers deposited on the sides of the mesa over the barrier layer in the order: (i) n-type semiconductor; (ii) semi-insulating material; and (iii) n-type semiconductor.
4. A semiconductor device comprising:
a first cladding layer formed on a substrate;
a multiple quantum well structure formed between the first cladding layer and a second cladding layer, the first cladding layer, the multiple quantum well structure and the second cladding layer being processed to form a mesa;
a barrier layer deposited on the sides of the mesa, wherein the barrier layer comprises semiconductor material and an n-type dopant selected from the group consisting of sulfur, silicon, selenium, copper and tin; and
overgrowth layers deposited on the sides of the mesa over the barrier layer in the order: (i) n-type semiconductor; (ii) p-type semiconductor; (iii) n-type semiconductor; (iv) semi-insulating material; and (v) n-type semiconductor.
5. A semiconductor device according to claim 1 , wherein the device further comprises a first confinement layer and a second confinement layer, the first confinement layer being situated between the first cladding layer and the multiple quantum well structure and the second confinement layer being situated between the multiple quantum well structure and the second cladding layer.
6. A semiconductor device according to claim 3 , wherein the barrier layer comprises indium phosphide.
7. A semiconductor device according to claim 3 , wherein the device further comprises a first confinement layer and a second confinement layer, the first confinement layer being situated between the first cladding layer and the multiple quantum well structure and the second confinement layer being situated between the multiple quantum well structure and the second cladding layer.
8. A semiconductor device according to claim 4 , wherein the barrier layer comprises indium phosphide.
9. A semiconductor device according to claim 4 , wherein the device further comprises a first confinement layer and a second confinement layer, the first confinement layer being situated between the first cladding layer and the multiple quantum well structure and the second confinement layer being situated between the multiple quantum well structure and the second cladding layer.