IP Library Granted Patent US 7,041,559
Granted Patent B2
US 7,041,559 · App. 10/936,757 · Granted May 9, 2006

Methods of forming power semiconductor devices having laterally extending base shielding regions

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Quick Facts
Patent No.
US 7,041,559
App. No.
10/936,757
Granted
May 9, 2006
Kind
B2
Abstract

Methods of forming power semiconductor devices include forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate. A gate electrode is formed on the first surface. Base and base shielding region dopants are implanted into the transition region using the gate electrode as an implant mask. A plurality of annealing steps are performed so that the base shielding region dopants are driven in laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width.

Claims (15)

1. A method of forming a vertical power device, comprising the steps of:

forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate;

forming a gate electrode on the first surface;

implanting base shielding region dopants of second conductivity type at a relatively high dose and high energy level into an upper portion of the transition region, using the gate electrode as an implant mask;

annealing the semiconductor substrate to partially drive the base shielding region dopants vertically into the transition region and laterally underneath the gate electrode and thereby define first and second intermediate shielding regions;

implanting base region dopants of second conductivity type at a relatively low dose and low energy level into the first and second intermediate shielding regions, using the gate electrode as an implant mask;

annealing the semiconductor substrate to drive the base region dopants vertically into the substrate and laterally along the first surface and underneath the gate electrode to thereby define first and second base regions, and simultaneously drive the base shielding region dopants laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width; and

forming first and second source regions in the first and second base regions, respectively.

2. A method of forming a vertical power device, comprising the steps of:

forming a semiconductor substrate having a drift region of first conductivity type therein and a transition region of first conductivity type that extends between the drift region and a first surface of the semiconductor substrate;

forming a gate electrode on the first surface;

implanting base shielding region dopants of second conductivity type at a relatively high dose and high energy level into an upper portion of the transition region, using the gate electrode as an implant mask;

implanting base region dopants of second conductivity type at a relatively low dose and low energy level into the semiconductor substrate, using the gate electrode as an implant mask;

annealing the semiconductor substrate to drive the base region dopants vertically into the substrate and laterally along the first surface and underneath the gate electrode to thereby define first and second base regions, and simultaneously drive the base shielding region dopants laterally and vertically to substantially their full and final depth within the substrate and thereby define first and second base shielding regions that constrict a neck of the transition region to a minimum width; and

forming first and second source regions in the first and second base regions, respectively.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: SILICON PATENT HOLDINGS
Reel/Frame 057952/0858 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2021
From: SILICON PATENT HOLDINGS
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057034/0109 →
PATENT SECURITY AGREEMENT Recorded Sep 19, 2016
From: SILICON PATENT HOLDINGS
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 040074/0772 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY PREVIOUSLY RECORDED AT REEL: 024411 FRAME: 0724. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME . Recorded Aug 29, 2016
From: SILICON SEMICONDUCTOR CORPORATION
To: SILICON PATENT HOLDINGS
Reel/Frame 039861/0772 →
CORRECTIVE ASSIGNMENT TO CORRECT THE RECEIVING PARTY PREVIOUSLY RECORDED AT REEL: 024411 FRAME: 0728. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 29, 2016
From: SILICON SEMICONDUCTOR CORPORATION
To: SILICON PATENT HOLDINGS
Reel/Frame 039861/0850 →