IP Library Granted Patent US 7,074,115
Granted Patent B2
US 7,074,115 · App. 10/937,914 · Granted Jul 11, 2006

Polishing pad

Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
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Quick Facts
Patent No.
US 7,074,115
App. No.
10/937,914
Granted
Jul 11, 2006
Kind
B2
Abstract

A polishing pad is useful planarizing semiconductor substrates. The polishing pad comprises a polymeric material having a porosity of at least 0.1 volume percent, a KEL energy loss factor at 40° C. and 1 rad/sec of 385 to 750 1/Pa and a modulus E′ at 40° C. and 1 rad/sec of 100 to 400 MPa.

Claims (30)

1. A polishing pad useful for planarizing semiconductor substrates, the polishing pad comprising a polyurethane polymeric material having a porosity of at least 0.1 volume percent, the polyurethane polymeric material being formed from a prepolymer reaction product of toluene diisocyanate and polytetramethylene ether glycol with 4,4′-methylene-bis-o-chloroaniline and the prepolymer reaction product having a 5.5 to 8.6 weight percent NCO and an NH 2 to NCO stoichiometric ratio of 80 to 110 percent.

2. The polishing pad of claim 1 wherein the prepolymer reaction product has a 6.3 to 8.5 weight percent NCO.

3. The polishing pad of claim 1 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 385 to 750 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 100 to 400 MPa.

4. The polishing pad of claim 1 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 395 to 700 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 120 to 350 MPa.

5. The polishing pad of claim 1 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 405 to 600 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 140 to 300 MPa.

6. The polishing pad of claim 1 wherein the an NH 2 to NCO stoichiometric ratio of 80 to 100 percent.

7. The polishing pad of claim 1 wherein the polyurethane has a cross-linked structure.

8. The polishing pad of claim 1 wherein the polymeric material is polyurethane and the polymeric material has a density of 0.5 to 1.05 g/cm 3 .

9. The polishing pad of claim 8 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 385 to 750 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 100 to 400 MPa.

10. The polishing pad of claim 8 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 395 to 700 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 120 to 350 MPa.

11. The polishing pad of claim 8 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 405 to 600 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 140 to 300 MPa.

12. The polishing pad of claim 8 wherein the an NH 2 to NCO stoichiometric ratio of 80 to 100 percent.

13. The polishing pad of claim 8 wherein the polyurethane has a cross-linked structure.

14. The polishing pad of claim 8 wherein the polymeric material is polyurethane and the polymeric material has a density of 0.5 to 1.05 g/cm 3 .

15. A polishing pad useful for planarizing semiconductor substrates, the polishing pad comprising a polyurethane polymeric material having a porosity of at least 0.1 volume percent, the polyurethane polymeric material being formed from a prepolymer reaction product of toluene diisocyanate and polytetramethylene ether glycol with 4,4′-methylene-bis-o-chloroaniline and the prepolymer reaction product having a 6.3 to 8.5 weight percent NCO and an NH 2 to NCO stoichiometric ratio of 80 to 110 percent and a Shore D hardness of 20 to 60.

16. A method of polishing a semiconductor substrate including the step of polishing the semiconductor substrate with a polishing pad useful for planarizing semiconductor substrates, the polishing pad comprising a polyurethane polymeric material having a porosity of at least 0.1 volume percent, the polyurethane polymeric material being formed from a prepolymer reaction product of toluene diisocyanate and polytetramethylene ether glycol with 4,4′-methylene-bis-o-chloroaniline and the prepolymer reaction product having a 6.3 to 8.5 weight percent NCO and an NH 2 to NCO stoichiometric ratio of 80 to 110 percent and a shore hardness of 20 to 60.

17. The method of claim 16 wherein the prepolymer reaction product has a 6.3 to 8.5 weight percent NCO.

18. The method of claim 16 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 385 to 750 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 100 to 400 MPa.

19. The method of claim 16 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 395 to 700 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 120 to 350 MPa.

20. The method of claim 16 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 405 to 600 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 140 to 300 MPa.

21. The method of claim 16 wherein the an NH 2 to NCO stoichiometric ratio of 80 to 100 percent.

22. The method of claim 16 wherein the polyurethane has a cross-linked structure.

23. The method of claim 16 wherein the polymeric material is polyurethane and the polymeric material has a density of 0.5 to 1.05 g/cm 3 .

24. A method of polishing a semiconductor substrate including the step of polishing the semiconductor substrate with a polishing pad useful for planarizing semiconductor substrates, the polishing pad comprising a polyurethane polymeric material having a porosity of at least 0.1 volume percent, the polyurethane polymeric material being formed from a prepolymer reaction product of toluene diisocyanate and polytetramethylene ether glycol with 4,4′-methylene-bis-o-chloroaniline and the prepolymer reaction product having a 6.3 to 8.5 weight percent NCO and an NH 2 to NCO stoichiometric ratio of 80 to 110 percent and a Shore D hardness of 20 to 60.

25. The method of claim 24 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 385 to 750 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 100 to 400 MPa.

26. The method of claim 24 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 395 to 700 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 120 to 350 MPa.

27. The method of claim 24 wherein the polishing pad comprises a polymeric material having a KEL energy loss factor at 40° C. and 1 rad/sec of 405 to 600 1/Pa, a modulus E′ at 40° C. and 1 rad/sec of 140 to 300 MPa.

28. The method of claim 24 wherein the an NH 2 to NCO stoichiometric ratio of 80 to 100 percent.

29. The method of claim 24 wherein the polyurethane has a cross-linked structure.

30. The method of claim 24 wherein the polymeric material is polyurethane and the polymeric material has a density of 0.5 to 1.05 g/cm 3 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 27, 2005
From: JAMES, DAVID B.; KULP, MARY JO
To: ROHM AND HAAS ELECTRONIC MATERIALS CMP HOLDINGS, INC.
Reel/Frame 015627/0354 →
Continuity (2)
Continuation In Part 1068215800 · Oct 9, 2003
Related Publication 20050079806A1 · Apr 14, 2005