Semiconductor device with copper wirings having improved negative bias temperature instability (NBTI)
View Patent ↗A semiconductor device with p-channel MOS transistor having: a gate insulating film of nitrogen-containing silicon oxide; a gate electrode of boron-containing silicon; side wall spacers on side walls of the gate electrode, comprising silicon oxide; an interlayer insulating film having a planarized surface; a wiring trench and a contact via hole formed in the interlayer insulating film; a copper wiring pattern including an underlying barrier layer and an upper level copper region, and filled in the wiring trench; and a silicon carbide layer covering the copper wiring pattern. A semiconductor device has the transistor structure capable of suppressing NBTI deterioration.
1. A semiconductor device comprising:
a silicon substrate having an n-type region;
a gate insulating film formed on the n-type region, using nitrogen-containing silicon oxide;
a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon;
p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode;
side wall spacers formed on side walls of said gate electrode, said side wall spacer comprising a lamination of a silicon oxide layer and a silicon nitride layer;
a lower interlayer insulating film having a planarized surface and covering said gate electrode and side wall spacers;
an intermediate interlayer insulating film formed above said lower interlayer insulating film, and having a planarized surface:
a wiring trench formed in said interlayer insulating film from the planarized surface to an inside thereof; and
a copper wiring pattern including an underlying barrier layer of Ta or Ti formed on inner surfaces of the wiring trench, and an upper level copper region formed on the underlying barrier layer, said copper wiring pattern being filled in said wiring trench, while being separated from the lower and intermediate interlayer insulating film.
2. A semiconductor device according to claim 1 , further comprising a copper-diffusion-preventing insulator layer formed on said copper wiring pattern and said interlayer insulating film.
3. A semiconductor device according to claim 2 , wherein said copper-diffusion-preventing insulator layer is made of silicon nitride.
4. A semiconductor device according to claim 3 , wherein said silicon nitride is formed by plasma-enhanced CVD using silane and ammonia as source gases.
5. A semiconductor device according to claim 4 , wherein said plasma-enhanced CVD is carried out with significantly reduced silane flow rate compared to standard condition.
6. A semiconductor device according to claim 1 , further comprising:
a via hole penetrating through said lower interlayer insulating film; and
a conductive plug filled in the via hole,
wherein said copper wiring is connected to said conductive plug at a bottom thereof.
7. A semiconductor device according to claim 6 , wherein said conductive plug comprises a lamination structure of a barrier metal and a tungsten layer.
8. A semiconductor device according to claim 1 , wherein said silicon nitride layer of said side wall spacer is formed on the side wall of the gate electrode, and said silicon oxide layer is formed thereon.
9. A semiconductor device comprising:
a silicon substrate having an n-type region;
a gate insulating film formed on the n-type region, using nitrogen-containing silicon oxide;
a gate electrode formed on said gate insulating film, said gate electrode comprising boron-containing silicon;
p-type source/drain regions formed in a surface layer of said silicon substrate on both sides of said gate electrode;
side wall spacers formed on side walls of said gate electrode, said side wall spacer comprising a lamination of an upper silicon oxide layer and a lower silicon nitride layer;
a lower interlayer insulating film having a planarized surface and covering said gate electrode and side wall spacers;
conductive plugs penetrating through the lower interlayer insulating film;
an intermediate interlayer insulating film formed above said lower interlayer insulating film, and having a planarized surface;
a wiring trench formed in said interlayer insulating film from the planarized surface to expose one of said conductive plugs;
a copper wiring pattern including an underlying barrier layer of Ta or Ti formed on inner surfaces of the wiring trench, and an upper level copper region formed on the underlying barrier layer, said copper wiring pattern having a planarized surface, and being filled in said wiring trench, while being separated from the lower and intermediate interlayer insulating film; and
a copper-diffusion-preventing insulator layer made of silicon nitride, and formed on said copper wiring pattern and said interlayer insulating film.
10. A semiconductor device according to claim 9 , wherein said underlying barrier layer is formed of Ta.