System and method for a programmable gain amplifier
View Patent ↗Provided is system for an improved programmable gain amplifier (PGA). The system includes an amplifier and a first gain control mechanism. The first gain control mechanism includes a circuit input port and is positioned along a feedback path of the amplifier. The first gain control mechanism is configured to (i) receive an input signal and (ii) moderate gains applied to the received input signal, the applied gains including gain values of greater than or equal to one. A second gain control mechanism is coupled to the first gain control mechanism and is integrated with a function of the amplifier. The second gain control mechanism (i) provides gain values of less than one and (ii) decreases a feedback factor of the amplifier when the gain values are provided having values of less than one.
1. A circuit comprising:
an amplifier;
a first gain control mechanism including a circuit input port and positioned along a feedback path of the amplifier;
a second gain control mechanism coupled to the first gain control mechanism and integrated with a function of the amplifier;
wherein the first and second gain control mechanisms are switch networks;
wherein the first gain control mechanism includes a first and second portion, the first portion including a first portion impedance device, the second portion including a number of switches and second portion impedance devices, the first portion impedance device having a first end forming the first circuit input port and a second end coupled to a first end of a first of the second portion impedance devices; and
wherein the second gain control mechanism includes a switch and two or more impedance devices connected in series, the switch being connected between the two or more impedance devices, open ends of the two or more impedance devices being respectively connected to the second ends of the respective first portion impedance devices.
2. The circuit of claim 1 , wherein the second gain control mechanism is a passive attenuator.
3. The circuit of claim 1 , wherein the gain values of the second gain control mechanism are provided via selective control of the switches.
4. The circuit of claim 3 , wherein the amplifier and the gain control mechanisms are formed using a CMOS process.