Direct current cut structure
In the direct current cut structure of the present invention, two capacitors are provided in parallel between signal transmission line patterns facing each other on a substrate, and each of the two capacitors is electrically connected to each surface of each transmission line pattern that is exposed through a hole part provided on the substrate. It is preferable for the two capacitors to have different capacity. If there is no need to cover such a broad band, only one capacitor can also connected to either side of each transmission line pattern exposed through the hole part.
1. A direct current cut structure in which two capacitors are provided in parallel between signal transmission line patterns facing each other on a substrate, wherein
the two capacitors are electrically connected to each surface of each transmission line pattern that is exposed through a hole part provided on the substrate.
2. The direct current cut structure according to claim 1 , wherein the two capacitors have different capacity values.
3. The direct current cut structure according to claim 1 , wherein
the two capacitors both are ceramic capacitors.
4. The direct current cut structure according to claim 1 , wherein
a co-planar line in which a ground pattern is provided on a surface provided with transmission line patterns in such a way as to pinch the transmission line patterns is applied to pattern disposition.
5. The direct current cut structure according to claim 1 , wherein
a co-planar line in which a ground pattern is provided on a surface provided with transmission line patterns in such a way as to pinch the transmission line patterns is used as patterns of a predetermined section including a capacitor connection part on the substrate.
6. The direct current cut structure according to claim 5 , wherein
a conversion part to a micro-strip line in which transmission line patterns and a ground pattern are provided on one and the other surfaces, respectively, is provided in an end part excluding a predetermined section on the substrate from the co-planar line.
7. The direct current cut structure according to claim 5 , wherein
a conversion part to a grounded co-planar line in which transmission line patterns are provided on one surface and a ground pattern is provided on each surface, respectively, is provided in an end part excluding the predetermined section on the substrate from the co-planar line.
8. The direct current cut structure according to claim 5 , wherein
a flying lead is provided in an end part excluding a predetermined section on the substrate.
9. The direct current cut structure according to claim 8 , wherein
at least a part of the pattern width of a flying lead part of the end part is matched with the pattern width on a substrate of a connection party.
10. The direct current cut structure according to claim 1 , wherein
the respective capacity of the two capacitors is set to the same value.
11. The direct current cut structure according to claim 1 , wherein
the width of each of the transmission line pattern is set between the respective widths of the two capacitors.
12. The direct current cut structure according to claim 1 , wherein
one of a co-planar line in which a ground pattern is provided in such a way as to pitch the transmission line patterns, a micro-strip line in which transmission line patterns and ground pattern are provided on one and the other surfaces and a grounded co-planar line in which transmission line patterns are provided on one surface and a ground pattern is provided on each surface, is used as the pattern disposition of the predetermined section including a capacitor connection part on the substrate.
13. The direct current cut structure according to claim 12 , wherein
a conversion part to another pattern different from a used pattern is provided in the end part excluding the predetermined section on the substrate from the pattern used in the predetermined section.
14. A direct current cut structure in which one capacitor is provided between signal transmission line patterns facing each other on a substrate, wherein
the capacitor is electrically connected to either surface of each transmission line pattern that is exposed through a hole part provided on the substrate.
15. A radio frequency (RF) circuit substrate in which the direct current cut structure set forth in claim 1 is used on an RF signal line.
16. An IC package in which the direct current cut structure set forth in claim 1 is used on the RF signal line of an interposer on which ICs are mounted.
17. A manufacturing method of a circuit substrate including a direct current cut structure in which two capacitors are provided in parallel between signal transmission line patterns facing each other on a substrate, comprising:
providing a hole part for a connection part of two capacitors on the substrate;
exposing a part of each of the transmission line patterns through the hole part and mounting each of the transmission line patterns on the substrate; and
electrically connecting each of the capacitors to each surface of the exposed part of each of the transmission line patterns, and
a manufacturing process of a flexible substrate is used as the mounting process.
18. A manufacturing method of a circuit substrate including a direct current cut structure in which one capacitor is provided between signal transmission line patterns facing each other on a substrate, comprising:
providing a hole part for a connection part of two capacitors on the substrate;
exposing a part of each of the transmission line patterns through the hole part and mounting each of the transmission line patterns on the substrate; and
electrically connecting the capacitor to either surface of the exposed part of each of the transmission line patterns, and
a manufacturing process of a flexible substrate is used as the mounting process.
19. A radio frequency (RF) circuit substrate in which the direct current cut structure set forth in claim 14 is used on an RF signal line.
20. An IC package in which the direct current cut structure set forth in claim 14 is used on the RF signal line of an interposer on which ICs are mounted.