Apparatuses, computer program product and method for bit rate control of digital image encoder

1 . A bit rate controller for a digital image encoder, comprising:

a target cumulative distribution function computing mechanism predicting the number of encoded bits resulting from an encoding to be performed in the encoder;

a counter mechanism counting the number of encoded bits resulting from the encoding;

a check mechanism forming an error term from a comparison between a value of the counter and a corresponding value of the target cumulative distribution function; and

a bit rate control mechanism adjusting a quantization parameter of the encoding to be continued on the basis of the error term.

2 . The bit rate controller of claim 1 , wherein the target cumulative distribution function computing mechanism comprises a target linear cumulative distribution function computed in a non-correlating situation.

3 . The bit rate controller of claim 2 , wherein the non-correlating situation comprises at least one of encoding of a first frame, and a discontinuous point in encoding.

4 . The bit rate controller of claim 2 , wherein the check mechanism operates at predetermined checkpoints during the encoding, and wherein the target linear cumulative distribution function T i for a checkpoint i is

T i =( ba n /N )* C i ,

where ba n is a bit load allocated to a frame n, N is the number of the checkpoints, and C i is a number of a macro block at the checkpoint i.

5 . The bit rate controller of claim 1 , wherein the target cumulative distribution function computing mechanism comprises a target adaptive cumulative distribution function computed in a correlating situation.

6 . The bit rate controller of claim 5 , wherein the correlating situation comprises encoding of correlating consecutive intra or inter frames.

7 . The bit rate controller of claim 5 , wherein the check mechanism operates at predetermined checkpoints during the encoding, and wherein the target adaptive cumulative distribution function Ti for a checkpoint i is

T i =( ba n /bl n−1 )* bl n−1 ( i ),

where ba n is a bit load allocated to a frame n, and bl n−1 (i) is a bit load at the checkpoint i of a previous frame n−1.

8 . The bit rate controller of claim 1 , wherein the check mechanism operates at predetermined checkpoints during the encoding.

9 . The bit rate controller of claim 8 , wherein the target cumulative distribution function computing mechanism operates at the checkpoint.

10 . The bit rate controller of claim 8 , wherein the predetermined checkpoints comprise predetermined transition points between two successive macro blocks.

11 . An arrangement for bit rate control in a digital image encoder, comprising:

means for computing a target cumulative distribution function predicting the number of encoded bits resulting from an encoding to be performed in the encoder;

means for counting the number of encoded bits resulting from the encoding;

means for forming an error term from a comparison between a value of the counter and a corresponding value of the target cumulative distribution function; and

means for bit rate control by adjusting a quantization parameter of the encoding to be continued on the basis of the error term.

12 . A computer program product for bit rate control of a digital image encoder, comprising:

a target cumulative distribution function computing module predicting the number of encoded bits resulting from an encoding to be performed in the encoder;

a counter module counting the number of encoded bits resulting from the encoding;

a check module forming an error term from a comparison between a value of the counter and a corresponding value of the target cumulative distribution function; and

a bit rate control module adjusting a quantization parameter of the encoding to be continued on the basis of the error term.

13 . The computer program product of claim 12 , wherein the computer program product is embodied on a distribution medium readable by a computer.

14 . The computer program product of claim 13 , wherein the distribution medium comprises at least one of a computer readable program storage medium, a computer readable memory, a computer readable software distribution package, a computer readable signal, a computer readable telecommunications signal.

15 . An integrated digital image encoding circuit comprising:

a target cumulative distribution function computing block predicting the number of encoded bits resulting from an encoding to be performed;

a counter block counting the number of encoded bits resulting from the encoding;

a check block forming an error term from a comparison between a value of the counter and a corresponding value of the target cumulative distribution function; and

a bit rate control block adjusting a quantization parameter of the encoding to be continued on the basis of the error term.

16 . A method for controlling a bit rate in a digital image encoder, comprising:

computing a target cumulative distribution function predicting the number of encoded bits resulting from an encoding to be performed in the encoder;

counting the number of encoded bits resulting from the encoding;

forming an error term from a comparison between a value-of the counter and a corresponding value of the target cumulative distribution function; and

controlling a bit rate by adjusting a quantization parameter of the encoding to be continued on the basis of the error term.