Method and system for minimizing both on-chip memory size and peak DRAM bandwidth requirements for multifield deinterlacers
View Patent ↗In a video system, a method and system for minimizing both on-chip memory size and peak DRAM bandwidth requirements for multi-field deinterlacers are provided. Present line pixels and absent line pixels may be determined and may be ordered into upper line pixels and lower line pixels based on whether an interlaced output frame is top field or bottom field originated. Upper line pixels may be buffered in an upper line FIFO that may hold half a video line and lower line pixels may be buffered in an lower line FIFO that may hold a video line. A source switch and a line length counter may be used to assemble the deinterlaced output frame by selecting from the buffered upper line pixels and the buffered lower line pixels. The deinterlaced output frame may be buffered in an output FIFO.
1. A method for video signal processing, the method comprising:
buffering a plurality of upper line pixels and a plurality of lower line pixels, wherein said upper line pixels or said lower line pixels comprise an absent line generated in a motion adaptive deinterlacer;
ordering said buffered plurality of upper line pixels and said buffered plurality of lower line pixels; and
generating a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels.
2. The method according to claim 1 , comprising buffering said plurality of upper line pixels for a half video line.
3. The method according to claims 1 , comprising buffering said plurality of lower line pixels for a video line.
4. The method according to claim 1 , comprising generating a plurality of present line pixels and a plurality of absent line pixels.
5. The method according to claim 1 , comprising ordering said buffered plurality of upper line pixels by selecting N of said buffered plurality of upper line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
6. The method according to claim 1 , comprising ordering said buffered plurality of lower line pixels by selecting N of said buffered plurality of lower line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
7. The method according to claim 1 , comprising generating said deinterlaced output frame by alternatively selecting between N of said buffered plurality of upper line pixels and N of said buffered plurality of lower line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
8. The method according to claim 1 , comprising buffering said plurality of upper line pixels for a half video line.
9. The method according to claim 1 , comprising buffering said plurality of lower line pixels for a video line.
10. A machine-readable storage having stored thereon, a computer program having at least one code section for video signal processing, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
buffering a plurality of upper line pixels and a plurality of lower line pixels, wherein said upper line pixels or said lower line pixels comprise an absent line generated in a motion adaptive deinterlacer;
ordering said buffered plurality of upper line pixels and said buffered plurality of lower line pixels; and
generating a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels.
11. The machine-readable storage according to claim 10 , comprising code for generating a plurality of present line pixels and a plurality of absent line pixels.
12. The machine-readable storage according to claim 10 , comprising code for ordering said buffered plurality of upper line pixels by selecting N of said buffered plurality of upper line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
13. The machine-readable storage according to claim 10 , comprising code for ordering said buffered plurality of lower line pixels by selecting N of said buffered plurality of lower line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
14. The machine-readable storage according to claim 10 , comprising code for generating said deinterlaced output frame by alternatively selecting between N of said buffered plurality of upper line pixels and N of said buffered plurality of lower line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
15. A system for video signal processing, the system comprising:
a pixel processor that buffers a plurality of upper line pixels and a plurality of lower line pixels, wherein said upper line pixels or said lower line pixels comprise an absent line generated in a motion adaptive deinterlacer;
said pixel processor orders said buffered plurality of upper line pixels and said buffered plurality of lower line pixels; and
said pixel processor generates a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels.
16. The system according to claim 15 , wherein said pixel processor comprises a pixel computation.
17. The system according to claim 16 , wherein said pixel computation generates a plurality of present line pixels and a plurality of absent line pixels.
18. The system according to claim 15 , wherein said pixel processor comprises a line reorder.
19. A method for video signal processing, the method comprising: buffering a plurality of upper line pixels and a plurality of lower line pixels;
ordering said buffered plurality of upper line pixels and said buffered plurality of lower line;
generating a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels; and
generating a plurality of present line pixels and a plurality of absent line pixels after cross chrominance removal.
20. A method for video signal processing, the method comprising:
buffering a plurality of upper line pixels and a plurality of lower line pixels;
ordering said buffered plurality of upper line pixels and said buffered plurality of lower line;
generating a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels;
generating a plurality of present line pixels and a plurality of absent line pixels; and
transferring said plurality of present line pixels to said plurality of lower line pixels and said plurality of absent line pixels to said plurality of upper line pixels when said deinterlaced output frame is originated from a bottom field.
21. A method for video signal processing, the method comprising:
buffering a plurality of upper line pixels and a plurality of lower line pixels;
ordering said buffered plurality of upper line pixels and said buffered plurality of lower line;
generating a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels;
generating a plurality of present line pixels and a plurality of absent line pixels; and
transferring said plurality of present line pixels to said plurality of upper line pixels and said plurality of absent line pixels to said plurality of lower line pixels when said deinterlaced output frame is originated from a top field.
22. A machine-readable storage having stored thereon, a computer program having at least one code section for video signal processing, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
buffering a plurality of upper line pixels and a plurality of lower line pixels;
ordering said buffered plurality of upper line pixels and said buffered plurality of lower line pixels;
generating a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels; and
generating a plurality of present line pixels and a plurality of absent line pixels after cross chrominance removal.
23. A machine-readable storage having stored thereon, a computer program having at least one code section for video signal processing, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
buffering a plurality of upper line pixels and a plurality of lower line pixels;
ordering said buffered plurality of upper line pixels and said buffered plurality of lower line pixels;
generating a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels;
generating a plurality of present line pixels and a plurality of absent line pixels; and
transferring said plurality of present line pixels to said plurality of lower line pixels and said plurality of absent line pixels to said plurality of upper line pixels when said deinterlaced output frame is originated from a bottom field.
24. A machine-readable storage having stored thereon, a computer program having at least one code section for video signal processing, the at least one code section being executable by a machine for causing the machine to perform steps comprising:
buffering a plurality of upper line pixels and a plurality of lower line pixels;
ordering said buffered plurality of upper line pixels and said buffered plurality of lower line pixels;
generating a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels;
generating a plurality of present line pixels and a plurality of absent line pixels; and
transferring said plurality of present line pixels to said plurality of upper line pixels and said plurality of absent line pixels to said plurality of lower line pixels when said deinterlaced output frame is originated from a top field.
25. A system for video signal processing, the system comprising:
a pixel processor that buffers a plurality of upper line pixels and a plurality of lower line pixels;
said pixel processor orders said buffered plurality of upper line pixels and said buffered plurality of lower line pixels; and
said pixel processor generates a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels;
said pixel processor comprises a pixel computation that generates a plurality of present line pixels and a plurality of absent line pixels; and
said pixel computation transfers said plurality of present line pixels to said plurality of lower line pixels and said plurality of absent line pixels to said plurality of upper line pixels when said deinterlaced output frame is originated from a bottom field.
26. A system for video signal processing, the system comprising:
a pixel processor that buffers a plurality of upper line pixels and a plurality of lower line pixels;
said pixel processor orders said buffered plurality of upper line pixels and said buffered plurality of lower line pixels; and
said pixel processor generates a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels;
said pixel processor comprises a pixel computation that generates a plurality of present line pixels and a plurality of absent line pixels; and
said pixel computation transfers said plurality of present line pixels to said plurality of upper line pixels and said plurality of absent line pixels to said plurality of lower line pixels when said deinterlaced output frame is originated from a top field.
27. A system for video signal processing, the system comprising:
a pixel processor that buffers a plurality of upper line pixels and a plurality of lower line pixels;
said pixel processor orders said buffered plurality of upper line pixels and said buffered plurality of lower line pixels; and
said pixel processor generates a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels; and
said pixel processor comprises a line reorder that generates said deinterlaced output frame by alternatively selecting between N of said buffered plurality of upper line pixels and N of said buffered plurality of lower line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
28. A system for video signal processing, the system comprising:
a pixel processor that buffers a plurality of upper line pixels and a plurality of lower line pixels;
said pixel processor orders said buffered plurality of upper line pixels and said buffered plurality of lower line pixels; and
said pixel processor generates a deinterlaced output frame from said ordered buffered plurality of upper line pixels and said ordered buffered plurality of lower line pixels; and
said pixel processor comprises a line reorder that comprises an upper line FIFO, a lower line FIFO, a source switch, and a line length counter.
29. The system according to claim 28 , wherein said upper line FIFO buffers said plurality of upper line pixels for a half video line.
30. The system according to claim 28 , wherein said lower line FIFO buffers said plurality of lower line pixels for a video line.
31. The system according to claim 28 , wherein said source switch selects N of said buffered plurality of upper line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
32. The system according to claim 28 , wherein said source switch selects N of said buffered plurality of lower line pixels, wherein N corresponds to a line length of said deinterlaced output frame.
33. The system according to claim 28 , wherein said line length counter counts a number N of pixels, wherein N corresponds to a line length of said deinterlaced output frame.