Overvoltage protection circuit of output MOS transistor

1. An overvoltage protection circuit for a circuit of an output MOS transistor and a load connected in series between a first power supply and a second power supply, comprising:

a drain and source of said output MOS transistor connected to said first power supply and load respectively;

a dynamic clamping circuit connected with a gate of said output MOS transistor;

a control switch connected between said first power supply and said dynamic clamping circuit; and

a surge detecting circuit configured to monitor voltage of said first power supply and turn off said control switch such that said dynamic clamping circuit does not operate when the voltage of said first power supply increases to a voltage higher than a predetermined voltage, and

wherein said first power supply has a positive potential relative to said second power supply, said output MOS transistor connected to said first power supply and said load connected to said second power supply.

2. The overvoltage protection circuit according to claim 1 , further comprising:

a control signal circuit connected between the gate of said output MOS transistor and said load.

3. The overvoltage protection circuit according to claim 2 , wherein said control signal circuit comprises:

a first resistance connected at a first end with said gate of said output MOS transistor, a second end of said first resistance being supplied a first control signal; and

a discharge switch connected between said second end of said first resistance and a node between said output MOS transistor and said load,

said output MOS transistor is turned on in response to said first control signal of a first logic level, and is turned off in response to said first control signal of a second logic level,

said discharge switch is turned on when said output MOS transistor is turned off, such that a charge of said gate of said output MOS transistor is discharged through said first resistance, and said discharge switch is turned off when said output MOS transistor is turned on.

4. The overvoltage protection circuit according to claim 1 , wherein said surge detecting circuit comprises:

a first diode which has a cathode connected with said first power supply and breaks down when the voltage of said first power supply increases to the voltage higher than the predetermined voltage;

a second resistance connected between an anode of said first diode and a third power supply;

a first inverter which inverts a logic level corresponding to a voltage at a node between said first diode and said second resistance; and

a second inverter which inverts an output of said first inverter such that said control switch is turned off when said first diode is broken down.

5. The overvoltage protection circuit according to claim 1 , wherein said dynamic clamping circuit comprises:

a zener diode which has a cathode connected with said first power supply; and

a diode connected between an anode of said zener diode and said gate of said output MOS transistor.

6. The overvoltage protection circuit according to claim 1 , wherein said output MOS transistor is formed by connecting a plurality of unit cell transistors in parallel, and has a second breakdown characteristic in a safe operation area.

7. A method of protecting an output MOS transistor, wherein said output MOS transistor and a load are connected in series between a first power supply and a second power supply, a drain and source of said output MOS transistor connected to said first power supply and load respectively, and a series circuit of a control switch and a dynamic clamping circuit is connected between said first power supply and a gate of said output MOS transistor, said method comprising:

monitoring voltage of said first power supply; and,

wherein said first power supply has a positive potential relative to said second power supply, said output MOS transistor connected to said first power supply and said load connected to said second power supply.

8. The method according to claim 7 , wherein said load is an inductive load,

said method further comprises:

disconnecting said gate of said output MOS transistor from a drain of said output MOS transistor when said output MOS transistor is turned on; and

connecting said gate of said output MOS transistor and said drain of said output MOS transistor through a resistance when said output MOS transistor is turned off, such that a charge of said gate of said output MOS transistor is discharged through said resistance.

9. The overvoltage protection circuit according to claim 7 , wherein said monitoring comprises:

setting a voltage of a first node to a high voltage when the voltage of said first power supply does not increase to the voltage higher than the predetermined voltage; and

setting a voltage of the first node to a low voltage when the voltage of said first power supply increases to the voltage higher than the predetermined voltage,

said turning off a control switch comprises:

turning off said control switch based on the low voltage of the first node.