Method of fabricating semiconductor device
View Patent ↗In a method of fabricating a semiconductor device having a MISFET of trench gate structure, a trench is formed from a major surface of a semiconductor layer of first conductivity type which serves as a drain region, in a depth direction of the semiconductor layer, a gate insulating film including a thermal oxide film and a deposited film is formed over the internal surface of the trench, and after a gate electrode has been formed in the trench, impurities are introduced into the semiconductor substrate of first conductivity type to form a semiconductor region of second conductivity type which serves as a channel forming region, and impurities are introduced into the semiconductor region of second conductivity type to form the semiconductor region of first conductivity type which serves as a source region.
1. A semiconductor device having a MISFETs forming region and a gate lead-out region on a main surface of a semiconductor substrate, comprising:
a plurality of first trenches in said semiconductor substrate in said MISFETS forming region;
a plurality of gate oxide films of said MISFETs formed in said plurality of first trenches;
a plurality of gate electrodes of said MISFETs formed on said plurality of gate oxide films;
a second trench formed in said gate lead-out region, said second trench being perpendicular to the first trenches;
a gate lead-out electrode formed in said second trench and outside the second trench in said gate lead-out region,
wherein said gate lead out region is located in a peripheral region of the main surface of said semiconductor substrate;
said gate lead-out electrode and gate electrodes are comprised of a same material;
said second trench is connected at an end portion of each of said first trenches;
said first trenches are terminated by said second trench; and
said plurality of gate electrodes are connected with said gate lead-out electrode.
2. A semiconductor device according to claim 1 , wherein said MISFETs forming region is located on only one side of said gate lead-out region.
3. A semiconductor device according to claim 1 , wherein said gate lead-out electrode and gate electrodes are comprised of a silicon film.
4. A semiconductor device according to claim 1 , wherein said plurality of gate electrodes are electrically connected.
5. A semiconductor device according to claim 1 , wherein a gate wiring is formed over said gate lead-out electrode, and
wherein said gate wiring electrode and gate lead-out electrode are electrically connected.
6. A semiconductor device according to claim 5 , wherein a source electrode is formed over said plurality of gate electrodes, and
wherein said source electrode is electrically connected with source regions of said MISFETs, formed on the main surface of said semiconductor substrate.
7. A semiconductor device according to claim 6 , wherein a drain electrode is formed on a back surface of said semiconductor substrate, and
wherein said drain electrode is electrically connected with a drain region of said MISFETs, formed in said semiconductor substrate.