Efficient multiplex conferencing engine
View Patent ↗A conference engine operates in a multiplex processing scheme and requires a signal hardware summer to process all of the programmed conferences, all of the outputs and all of the input channels. The conference engine is only limited by the number of available input channels, the number of desired conference registers, the speed of the implementation, and the amount of memory available on the target system. The conference engine allows the number of available conference channels, the number of conferences per bridge and the number of bridges to be scaled. Each bridge contains a unique set of conference registers and has full access to the input channel data. Additional conference bridges are added by increasing the operating clock/memory to meet the processing requirements of the additional bridge. Conference registers in each conference bridge can be added/removed depending on the system requirements and are independent of the number of input channels.
1. A conference engine comprising:
a copy buffer including a local copy of input channel data that is refreshed once per frame synchronization signal, said input data containing data to be utilized by said conference engine and containing channel control data that is ultimately passed to an output channel;
a summer, said summer including a single signed adder;
a plurality of bridges connected to an output of said summer;
an output buffer, said output buffer including processed output channel data updated once per frame synchronization signal; and
an access and control subsection, said access and control subsection to perform multiplexed conference operations and including connections to said copy buffer, said plurality of bridges, said summer, said output buffer, and to an external bus for conference control data.
2. The conference engine as claimed in claim 1 further including:
a front-end pipeline processor, said front-end pipeline processor providing linear encoded data to said conference engine;
a back-end pipeline processor; and
a register/memory GLU logic having memory registers utilized by said conference engine and programmed by a system user.
3. The conference engine as claimed in claim 1 wherein said copy buffer includes random access memory.
4. The conference engine as claimed in claim 1 wherein said plurality of bridges include dual ported random access memory.
5. The conference engine as claimed in claim 1 wherein said output buffer includes dual ported random access memory.