Method for manufacture of an epitaxial structural element layer sequence and optoelectronic semiconductor chip

1. A method for fabricating an epitaxial component layer sequence based on a first III/V compound semiconductor material system with a first group V element on a substrate or a buffer layer, the substrate or the buffer layer comprising a material based on a second III/V compound semiconductor material system with a second group V element, which is different from the first group V element,

wherein

at least one layer sequence with a first and a second III/V compound semiconductor material layer is applied to the substrate or to the buffer layer before the application of the epitaxial component layer sequence, the first and second III/V compound semiconductor material layers having different compositions from one another and containing both the first and the second group V elements, and

the first III/V compound semiconductor material layer has a quinternary composition and the second III/V compound semiconductor material layer has a ternary composition;

wherein

a plurality of layer sequences with in each case a first and a second III/V compound semiconductor material layer are applied to the substrate or to the buffer layer before the application of the epitaxial component layer sequence.

2. The method as claimed in claim 1 , wherein

the content of the second group V element in the plurality of layer sequences decreases on average in the direction from the substrate or from the buffer layer toward the epitaxial component layer sequence.

3. The method as claimed in claim 1 , wherein

the substrate is a GaAs substrate or a GaAs-based substrate, the component layer sequence is an In x Ga y Al 1−x−y P-based III/V compound semiconductor layer sequence where 0≦x≦1, 0≦y≦1 and x+y≦1 and the first and second III/V compound semiconductor material layer(s) are In x Ga y Al 1−x−y As z P 1−z layers where 0≦x≦1, 0≦y≦1; x+y≦1 and 0<z<1.

4. The method as claimed in claim 1 , wherein

a plurality of layer sequences is provided, each layer sequence comprising an In x Ga y Al 1−x−y As z P 1−z layer where 0<x<1, 0<y≦1; x+y≦1 and 0<z<1 and a GaAs z P 1−z layer where 0<z<1, or consisting of an In x Ga y Al 1−x−y As z P 1−z layer where 0<x<1, 0<y<1; x+y≦1 and 0<z<1 and a GaAs z P 1−z layer where 0<z<1.

5. The method as claimed in claim 1 , wherein

the growth of the layer sequence(s) produces a ramplike transition from As-stabilized growth to P-stabilized growth.

6. The method as claimed in claim 1 , wherein

layer thicknesses of the first and second III/V compound semiconductor material layer(s) are between 1 nm and 50 nm inclusive.

7. An optoelectronic semiconductor chip with an epitaxial component layer sequence based on a first III/V compound semiconductor material system with a first group V element on a substrate or a buffer layer, the substrate or the buffer layer comprising a material based on a second III/V compound semiconductor material system with a second group V element, which is different from the first group V element,

wherein

at least one layer sequence with a first and a second III/V compound semiconductor material layer is arranged between the substrate or the buffer layer and the epitaxial component layer sequence, the first and second III/V compound semiconductor material layers having different compositions from one another and containing both the first and the second group V elements; and

the first III/V compound semiconductor material layer has a quinternary composition and the second III/V compound semiconductor material layer has a ternary composition;

wherein

provision is made of a plurality of layer sequences each having a first and and a second III/V compound semiconductor material layer.

8. The optoelectronic semiconductor chip as claimed in claim 7 , wherein the content of the second group V element in the plurality of layer sequences decreases on average in the direction from the substrate or from the buffer layer toward the epitaxial component layer sequence.

9. The optoelectronic semiconductor chip as claimed in claim 7 , wherein the substrate is a GaAs substrate or a GaAs-based substrate, the component layer sequence is an In x Ga y Al 1−x−y P-based III/V compound semiconductor layer sequence where 0≦x≦1, 0≦y≦1 and x+y≦1 and the first and second III/V compound semiconductor material layer(s) are In x Ga y Al 1−x−y As z P 1−z , layers where 0≦x≦1, 0≦y≦1; x+y≦1 and 0<z<1.

10. The optoelectronic semiconductor chip as claimed in claim 7 , wherein a plurality of layer sequences are provided, each layer sequence comprising an In x Ga y Al 1−x−y As z P 1−z layer where 0<x<1, 0<y≦1; x+y<1 and 0<z<1 and a GaAs z P 1−z layer where 0<z<1, or consisting of an In x Ga y Al 1−x−y As z P 1−z layer where 0<x<1, 0<y<1; x+y≦1 and 0<z<1 and a GaAs z P 1−z layer where 0<z<1.

11. The optoelectronic semiconductor chip as claimed in claim 7 , wherein the layer thicknesses of the first and second III/V compound semiconductor material layer(s) lie between 1 nm and 50 nm inclusive.