Multiplexer with low parasitic capacitance effects
View Patent ↗A differential multiplexer includes a plurality of multiplexing circuits. Each multiplexing circuit inputs a corresponding differential input signal including a positive input signal and a negative input signal, and outputs positive and negative output signals. Each multiplexing circuit includes first, second, third and fourth transistors. The first and second transistors input the positive input signal. The third and fourth transistors input the negative input signal. Outputs of the first and third transistors are connected to the positive output signal. Outputs of the second and fourth transistors are connected to the negative output signal. The positive and negative output signals are controlled using gate voltages on the first and fourth transistors. The second and third transistors are turned off when the differential multiplexer is in use. The transistors are cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals.
1. A differential multiplexer comprising:
a plurality of multiplexing circuits, each multiplexing circuit inputting a corresponding differential input signal including a positive input signal and a negative input signal, and outputting positive and negative output signals, and each multiplexing circuit comprising:
first, second, third and fourth transistors,
wherein the first and second transistors input the positive input signal,
wherein the third and fourth transistors input the negative input signal,
wherein outputs of the first and third transistors are connected to the positive output signal,
wherein outputs of the second and fourth transistors are connected to the negative output signal; and
wherein the positive output signals of the multiplexing circuits are coupled together at a first output node and the negative output signals are coupled together at a second output node.
2. The differential multiplexer of claim 1 , wherein the positive and negative output signals are controlled using gate voltages on the first and fourth transistors.
3. The differential multiplexer of claim 1 , wherein the second and third transistors are turned off when the differential multiplexer is in use.
4. A differential multiplexer comprising:
a plurality of multiplexing circuits;
each multiplexing circuit inputting a corresponding differential input signal including a positive input signal and a negative input signal, and outputting positive and negative output signals;
each multiplexing circuit comprising:
a plurality of transistors cross-coupled to make leakage between the positive and negative input signals common mode in the positive and negative output signals; and
wherein the positive output signals of the multiplexing circuits are coupled together at a first output node and the negative output signals are coupled together at a second output node.
5. The differential multiplexer of claim 4 , wherein each multiplexing circuit comprises:
first, second, third and fourth transistors,
wherein the first and second transistors input the positive input signal,
wherein the third and fourth transistors input the negative input signal,
wherein outputs of the first and third transistors are connected to the positive output signal,
wherein outputs of the second and fourth transistors are connected to the negative output signal.
6. The differential multiplexer of claim 5 , wherein the positive and negative output signals are controlled using gate voltages on the first and fourth transistors.
7. The differential multiplexer of claim 5 , wherein the second and third transistors are turned off when the differential multiplexer is in use.