Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
View Patent ↗A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
1. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with first patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate, with a first groove such that said first groove is formed in a region of said memory cell forming region uncovered by said first patterns, and with a second groove such that said second groove is formed in a region of said peripheral circuit region uncovered by said first patterns,
wherein said first groove and said second groove extend in said semiconductor substrate, and
wherein said second groove in said peripheral circuit region defines an active region of an MISFET in said peripheral circuit region;
(b) filling an insulating material in said first groove and said second groove such that a upper surface of said insulating material is higher than a main surface of said substrate;
(c) after said step (b), removing said first patterns in said peripheral circuit region and in said memory cell forming region;
(d) after said step (c), forming first conductor patterns in said peripheral circuit region, in said memory cell forming region and over said insulating material, such that said first conductor patterns are filled between insulating material in said memory cell forming region;
(e) forming an insulating film over said first conductor patterns;
(f) forming a conductive film over said insulating film; and
(g) patterning said conductive film and said first conductor patterns,
wherein, in said step (g), said conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (g), said first conductor patterns of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (g), said conductive film of said peripheral circuit region and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.
2. A method of manufacturing a semiconductor device according to claim 1 , wherein said first pattern is comprised of a silicon nitride film.
3. A method of manufacturing a semiconductor device according to claim 1 , further comprising the step of:
(h) between said step (e) and said step (f), forming an opening in said insulating film,
wherein, in said step (g), said conductive film of said peripheral circuit region is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.
4. A method of manufacturing a semiconductor device according to claim 1 , wherein said first patterns include an insulating film.
5. A method of manufacturing a semiconductor device according to claim 1 , wherein said first patterns include a conductive film and an insulating film formed over said conductive film, and wherein, in said step (c), said insulating film is removed so as to leave said conductive film.
6. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with first patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate, and with a first groove such that said first groove is formed in a region of said memory cell forming region uncovered by said first patterns and such that said first patterns cover said peripheral circuit region, wherein said first groove extends in said semiconductor substrate;
(b) filling an insulating material in said first groove such that an upper surface of said insulating material is higher than a main surface of said substrate;
(c) after said step (b), removing said first patterns in said peripheral circuit region and in said memory cell forming region;
(d) after said step (c), forming first conductor patterns over said main surface and over said insulating material such that said first conductor patterns are filled between insulating material in said memory cell forming region;
(e) forming an insulating film over said first conductor patterns;
(f) forming a conductive film over said insulating film; and
(g) patterning said conductive film and said first conductor patterns,
wherein, in said step (g), said conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (g), said first conductor patterns of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (g), said conductive film of said peripheral circuit region is patterned to form a gate electrode of an MISFET in said peripheral circuit region.
7. A method of manufacturing a semiconductor device according to claim 6 , wherein said first patterns are comprised of a silicon nitride film.
8. A method of manufacturing a semiconductor device according to claim 6 , wherein a second groove defining an active region of an MISFET in said peripheral circuit region is formed in a different manufacturing step from said first groove forming step.
9. A method of manufacturing a semiconductor device according to claim 6 , wherein said first patterns include an insulating film.
10. A method of manufacturing a semiconductor device according to claim 6 , wherein said first patterns include a conductive film and an insulating film formed over said conductive film, and wherein, in said step (c), said insulating film is removed so as to leave said conductive film.
11. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with first patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate, with a first groove such that said first groove is formed in a region of said memory cell forming region uncovered by said first patterns and such that said first groove extends in said semiconductor substrate, wherein said first groove of said memory cell forming region has a stripe shape extending in a first direction such that said first groove defines a distance between memory cells adjacent in a second direction crossing to said first direction;
(b) filling an insulating material in said first groove such that an upper surface of said insulating material is higher than a main surface of said substrate;
(c) after said step (b), removing said first patterns in said peripheral circuit region and in said memory cell forming region;
(d) after said step (c), forming first conductor patterns in said peripheral circuit region, in said memory cell forming region and over said insulating material such that said first conductor patterns are filled between said insulating material in said memory cell forming region;
(e) forming an insulating film over said first conductor patterns;
(f) forming a conductive film over said insulating film; and
(g) patterning said conductive film and said first conductor patterns,
wherein, in said step (g), said conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (g), said first conductor patterns of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (g), said conductive film of said peripheral circuit region and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode of an MISFET in said peripheral circuit region.
12. A method of manufacturing a semiconductor device according to claim 11 , wherein said first patterns include an insulating film.
13. A method of manufacturing a semiconductor device according to claim 11 , wherein said first patterns include a silicon nitride film.
14. A method of manufacturing a semiconductor device according to claim 11 , wherein said first patterns include a conductive film and an insulating film formed over said conductive film, and wherein, in said step (c), said insulating film is removed so as to leave said conductive film.
15. A method of manufacturing a semiconductor device according to claim 11 , further comprising the step of:
(h) between said step (e) and said step (f), forming an opening in said insulating film,
and wherein, in said step (g), said conductive film of said peripheral circuit region is patterned so as to be electrically connected to said gate electrode of said MISFET through said opening.
16. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with first patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate and with a first groove such that said first groove is formed in a region of said memory cell forming region uncovered by said first patterns and such that said first groove extends in said semiconductor substrate;
(b) filling an insulating material in said first groove such that an upper surface of said insulating material is higher than a main surface of said substrate;
(c) after said step (b), removing said first patterns in said peripheral circuit region and in said memory cell forming region;
(d) after said step (c), forming first conductor patterns over said main surface and over said insulating material such that said first conductor patterns are filled between insulating material in said memory cell forming region;
(e) forming an insulating film over said first conductor patterns;
(f) forming a conductive film over said insulating film; and
(g) patterning said conductive film and said first conductor patterns,
wherein, in said step (g), said conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (g), said first conductor patterns of said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (g), said conductive film of said peripheral circuit region is patterned to form a gate electrode of an MISFET in said peripheral circuit region.
17. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with first patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate, with first grooves such that said first grooves are formed in a region of said memory cell forming region uncovered by said first patterns and with a second groove such that said second groove is formed in a region of said peripheral circuit region uncovered by said first patterns,
wherein, in said memory cell forming region, said first grooves and said first patterns extend in a first direction such that said first grooves and said first patterns are arranged, in a second direction crossing said first direction, with each other,
wherein said second groove in said peripheral circuit region defines an active region of an MISFET in said peripheral circuit region, and
wherein said first grooves and said second groove extend in said semiconductor substrate;
(b) filling an insulating material in said first grooves and said second groove such that an upper surface of said insulating material is higher than a main surface of said substrate;
(c) after said step (b), removing said first patterns in said peripheral circuit region and in said memory cell forming region;
(d) after said step (c), forming first conductor patterns in said peripheral circuit region, in said memory cell forming region and over said insulating material such that said first conductor patterns are filled between insulating material in said memory cell forming region;
(e) forming an insulating film over said first conductor patterns;
(f) forming a conductive film over said insulating film; and
(g) patterning said conductive film and said first conductor patterns,
wherein, in said step (g), said conductive film of said memory cell forming region is patterned to form control gate electrodes of memory cells such that said control gate electrodes form word lines extending in said second direction,
wherein, in said step (g), said first conductor patterns of said memory cell forming region are patterned to form floating gate electrodes of said memory cells arranged in said first direction and in said second direction, and
wherein, in said step (g), said conductive film of said peripheral circuit region and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode of said MISFET in said peripheral circuit region.
18. A method of manufacturing a semiconductor device according to claim 17 , wherein said first patterns include an insulating film.
19. A method of manufacturing a semiconductor device according to claim 17 , wherein said first patterns include a silicon nitride film.
20. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with first patterns over a memory cell forming region and a peripheral circuit region of said semiconductor substrate, with a first groove such that said first groove is formed in a region of said memory cell forming region uncovered by said first patterns and such that said first groove extends in said semiconductor substrate,
wherein said first groove of said memory cell forming region has a stripe shape extending in a first direction such that said first groove defines a distance between memory cells adjacent in a second direction crossing to said first direction;
(b) filling an insulating material in said first groove such that an upper surface of said insulating material is higher than a main surface of said substrate;
(c) after said step (b), removing said first patterns in said peripheral circuit region and in said memory cell forming region;
(d) after said step (c), forming first conductor patterns in said peripheral circuit region, in said memory cell forming region and over said insulating material such that said first conductor patterns are filled between said insulating material in said memory cell forming region;
(e) forming an insulating film over said first conductor patterns;
(f) forming a conductive film over said insulating film; and
(g) patterning said conductive film and said first conductor patterns,
wherein, in said step (g), said conductive film of said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (g), said first conductor patterns of said memory cell forming region are patterned to form floating gate electrodes of said memory cells, and
wherein, in said step (g), said conductive film of said peripheral circuit region and said first conductor patterns of said peripheral circuit region are patterned to form a gate electrode of a MISFET in said peripheral circuit region.
21. A method of manufacturing a semiconductor device according to claim 20 , wherein said first patterns include an insulating film.
22. A method of manufacturing a semiconductor device according to claim 20 , wherein said first patterns include a silicon nitride film.
23. A method of manufacturing a semiconductor device according to claim 20 , wherein said first patterns include a conductive film and an insulating film formed over said conductive film, and wherein, in said step (c), said insulating film is removed so as to leave said conductive film.