Non-volatile semiconductor memory and method of making same, and semiconductor device and method of making device
View Patent ↗A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.
1. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with a first insulating film over a memory cell forming region, with a second insulating film formed over a peripheral circuit region, with first conductor patterns formed over said first insulating film and said second insulating film, and with grooves formed into said semiconductor substrate, in self-alignment with said first conductor patterns, at said memory cell forming region and at said peripheral circuit region, such that said grooves serve as an element isolation region in said memory cell forming region and in said peripheral circuit region,
wherein said second insulating film has a thickness greater than that of said first insulating film;
(b) filling third insulating films in said grooves at said memory cell forming region and at said peripheral circuit region by polishing an insulating film deposited over said memory cell forming region and said peripheral circuit region;
(c) after said step (b), forming second conductor patterns over said first conductor patterns;
(d) forming a fourth insulating film over said first conductor patterns;
(e) forming a conductive film over said fourth insulating film; and
(f) patterning said conductive film, said second conductor patterns and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,
wherein, in said step (f), said conductive film in said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (f), said first conductor patterns and said second conductor patterns in said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (f), said conductive film, said first conductor patterns and said second conductor patterns in said peripheral circuit region are patterned to form a gate electrode of a MISFET of said peripheral circuit region.
2. A method of manufacturing a semiconductor device according to claim 1 , wherein said second conductor patterns are formed to extend over said third insulating films.
3. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with a first insulating film over a memory cell forming region, with a second insulating film formed over a peripheral circuit region, and with first conductor patterns formed over said first insulating film and said second insulating film,
wherein said second insulating film has a thickness greater than that of said first insulating film;
(b) forming grooves into said semiconductor substrate, in self-alignment with said first conductor patterns, at said memory cell forming region and at said peripheral circuit region, such that said grooves serve as an element isolation region in said memory cell forming region and in said peripheral circuit region;
(c) filling third insulating films in said grooves at said memory cell forming region and at said peripheral circuit region by polishing an insulating film deposited over said memory cell forming region and said peripheral circuit region;
(d) after said step (c), forming second conductor patterns over said first conductor patterns;
(e) forming a fourth insulating film over said first conductor patterns;
(f) forming a conductive film over said fourth insulating film; and
(g) patterning said conductive film, said second conductor patterns and said first conductor patterns in said memory cell forming region and in said peripheral circuit region,
wherein, in said step (g), said conductive film in said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (g), said first conductor patterns and said second conductor patterns in said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (g), said conductive film, said first conductor patterns and said second conductor patterns in said peripheral circuit region are patterned to form a gate electrode of a MISFET of said peripheral circuit region.
4. A method of manufacturing a semiconductor device according to claim 3 , wherein said second conductor patterns are formed to extend over said third insulating films.
5. A method of manufacturing a semiconductor device, comprising steps of:
(a) providing a semiconductor substrate with a first insulating film over a memory cell forming region, with a second insulating film formed over a peripheral circuit region, with first conductor patterns formed over said first insulating film and said second insulating film, and with grooves formed into said semiconductor substrate, in self-alignment with said first conductor patterns, at said memory cell forming region and at said peripheral circuit region, such that said grooves serve as an element isolation region in said memory cell forming region and in said peripheral circuit region,
wherein said second insulating film has a thickness greater than that of said first insulating film;
(b) filling third insulating films in said grooves at said memory cell forming region and at said peripheral circuit region by polishing an insulating film deposited over said memory cell forming region and said peripheral circuit region;
(c) after said step (b), forming second conductor patterns at said memory cell forming region and at said peripheral circuit region;
(d) forming a fourth insulating film over said first conductor patterns;
(e) forming a conductive film over said fourth insulating film; and
(f) patterning said conductive film, and said second conductor patterns in said memory cell forming region and in said peripheral circuit region,
wherein, in said step (f), said conductive film in said memory cell forming region is patterned to form a control gate electrode of a memory cell,
wherein, in said step (f), said second conductor patterns in said memory cell forming region are patterned to form a floating gate electrode of said memory cell, and
wherein, in said step (f), said conductive film and said second conductor patterns in said peripheral circuit region are patterned to form a gate electrode of a MISFET of said peripheral circuit region.
6. A method of manufacturing a semiconductor device according to claim 5 , wherein said second conductor patterns are formed to extend over said third insulating films.
7. A method of manufacturing a semiconductor device according to claim 1 , wherein, in said step (a), a silicon nitride film is formed over each of said first conductor patterns,
wherein, in said step (b), said silicon nitride film serves as a stopper layer in said polishing, and
wherein, before said step (c), said silicon nitride film is removed.
8. A method of manufacturing a semiconductor device according to claim 3 , wherein, in said step (a), a silicon nitride film is formed over each of said first conductor patterns,
wherein in said step (c), said silicon nitride film serves as a stopper layer in said polishing, and
wherein, before said step (d), said silicon nitride film is removed.
9. A method of manufacturing a semiconductor device according to claim 5 , wherein, in step (a), a silicon nitride film is formed over each of said first conductor patterns,
wherein, in said step (b), said silicon nitride film serves as a stopper layer in said polishing, and
wherein, before said step (c), said silicon nitride film is removed.