Method for fabricating a semiconductor device
View Patent ↗A method for fabricating the semiconductor device includes forming linear field oxide regions on a semiconductor substrate; forming gate oxide lines on the semiconductor substrate between the field oxide regions; forming gate lines on the field oxide regions and the gate oxide lines, the gate lines being substantially perpendicular to the field oxide regions; etching the gate oxide lines and the field oxide regions between the gate lines; and forming a self-aligned source (SAS) region by injecting impurity ions into the etched regions, the impurity ion being injected in a direction at a predetermined angle other than 90° relative to the semiconductor substrate.
1. A method for fabricating a semiconductor device, comprising:
forming linear field oxide regions on a semiconductor substrate;
forming gate oxide lines on the semiconductor substrate between the field oxide regions;
forming gate lines on the field oxide regions and the gate oxide lines, wherein the gate lines extend in a direction perpendicular to the field oxide regions;
etching the gate oxide lines and the field oxide regions between the gate lines to form trenches, wherein a width of a top of the trenches is greater than a width of a bottom of the trenches; and
forming a self-aligned source (SAS) region by injecting impurity ions into the trenches, the impurity ion being injected in a direction at a predetermined angle other than 90° relative to the semiconductor substrate.
2. The method of claim 1 , wherein the impurity ions are injected in a direction at both a positive and a negative angle with respect to the semiconductor substrate and in a plane parallel with the gate line, wherein the positive angle is greater than 90° and the negative angle is less than 90°.
3. The method of claim 2 , wherein half of the impurity ions are injected in a positive angle direction and the other half of the impurity ions are injected in a negative angle.
4. The method of claim 1 , wherein the impurity ions are injected in a direction at an angle equal to or greater than 20° relative to the semiconductor substrate.
5. The method of claim 4 , wherein the angle is in a range of 20°˜55°.
6. The method of claim 1 , wherein the impurity ions are arsenic (As) ions.
7. The method of claim 6 , further comprising injecting phosphorous (P) ions in a vertical or tilted direction relative to the semiconductor substrate after the As ions are injected.
8. The method of claim 6 , wherein the amount of As ions injected is in a range of 5×10 14 ˜5×10 15 /cm 3 .
9. The method of claim 7 , wherein the amount of P ions injected is in a range of 1×10 14 ˜5×10 14 /cm 3 .
10. The method of claim 1 , wherein the field oxide regions are substantially parallel to a bit line of the device and the gate lines are substantially parallel to a word line of the device.
11. The method of claim 1 , wherein etching the gate oxide lines is performed using a mask exposing portions of the gate lines between the gate lines.
12. The method of claim 1 , wherein etching the gate oxide lines is carried out under a condition in that an etching speed of the field oxide regions is faster than an etching speed of the semiconductor substrate.
13. The method of claim 12 , wherein the field oxide regions comprise an oxide layer.
14. The method of claim 1 , wherein the gate lines comprise a first polycrystalline silicon layer, a dielectric layer, and a second polycrystalline silicon layer.