IP Library Granted Patent US 7,144,761
Granted Patent B2
US 7,144,761 · App. 10/958,282 · Granted Dec 5, 2006

Semiconductor device and method for fabricating the same

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Quick Facts
Patent No.
US 7,144,761
App. No.
10/958,282
Granted
Dec 5, 2006
Kind
B2
Abstract

A semiconductor device includes metal interconnects made from a multi-layer film composed of a first metal film formed on a semiconductor substrate with an insulating film sandwiched therebetween and a second metal film deposited on the first metal film. An interlayer insulating film having a via hole is formed on the metal interconnects. A third metal film is selectively grown on the second metal film within the via hole, so that a plug can be formed from the third metal film.

Claims (46)

1. A method for fabricating a semiconductor device comprising the steps of:

depositing a first metal film on a semiconductor substrate with an insulating film sandwiched therebetween;

depositing a second metal film on said first metal film;

forming an interlayer insulating film on said second metal film;

forming a via hole in said interlayer insulating film;

forming an adhesive layer on said via hole;

then, removing a part of said adhesive layer present on a bottom of said via hole selectively so as to expose a surface of said second metal film only at the bottom of said via hole;

forming a plug of a third metal film selectively grown on the exposed surface of said second metal film within said via hole;

forming a patterned interlayer insulating film by patterning said interlayer insulating film into the shape of interconnects; and

forming metal interconnects from a multi-layer film composed of said first metal film and said second metal film by etching said multi-layer film with said plug and said patterned interlayer insulating film used as a mask,

wherein said first metal film is an interconnected layer and said second metal film is a seed layer, and

said plug is in contact with said seed layer only at the bottom of said via hole.

2. The method for fabricating a semiconductor device of claim 1 ,

wherein said third metal film is grown by plating.

3. The method for fabricating a semiconductor device of claim 1 ,

wherein said second metal film and said third metal film are made from the same type of metal.

4. The method for fabricating a semiconductor device of claim 1 ,

wherein said second metal film and said third metal film are made from a metal including copper as a principal constituent, and

said third metal film is grown by plating an said second metal film with no adhesive layer sandwiched therebetween.

5. A semiconductor device, comprising:

metal interconnects formed on a semiconductor substrate with an insulating film sandwiched therebetween, and the metal interconnects including a first metal film of a lower layer and a second metal film of an upper layer;

an interlayer insulating film formed over the metal interconnects;

a via hole formed in the interlayer insulating film;

a plug made from a third metal film formed within the via hole,

wherein the first metal film is an interconnect Layer and the second metal film is a seed layer, and

the plug is in contact with said seed layer only at the bottom of said via hole.

6. The semiconductor device of claim 5 , further comprising an adhesive layer formed only on walls of the via hole.

7. The semiconductor device of claim 6 ,

wherein the adhesive layer is made of a silicon nitride film or a silicon carbide film.

8. The semiconductor device of claim 5 ,

wherein no seed layer is formed within the via hole.

9. The semiconductor device of claim 5 ,

wherein the interlayer insulating film is formed on the metal interconnects, and includes a patterned first interlayer insulating film and a second interlayer insulating film formed over the first interlayer insulating film.

10. A method for fabricating a semiconductor device comprising the steps of:

depositing first metal film on a semiconductor substrate with an insulating film sandwiched therebetween;

depositing a second metal film on said first metal film;

forming an interlayer insulating film on said second metal film;

forming a via hole in said interlayer insulating film so as to expose a surface of said second metal film only at the bottom of said via hole,

forming a plug of a third metal film selectively grown on the exposed surface of said second metal film within said via hole;

forming a patterned interlayer insulating film by patterning said interlayer insulating film into the shape of interconnects; and

forming metal interconnects from a multi-layer film composed of said first metal film and said second metal film by etching said multi-layer film with said plug and said patterned interlayer insulating film used as a mask,

wherein said first metal film is an interconnected layer and said second metal film is a seed layer, and

said plug is in contact with said seed layer only at the bottom of said via hole;

wherein the step of forming said via hole so as to expose the surface of said second metal film only at the bottom of said via hole includes the steps of:

depositing an adhesive layer over walls and the bottom of said via hole, and

performing an anisotropic etching with respect to said adhesive layer so as to have said adhesive layer only on the walls of said via hole.

Assignments (7)
RELEASE OF SECURITY INTEREST Recorded Oct 26, 2020
From: JEFFERIES FINANCE LLC
To: RPX CORPORATION
Reel/Frame 054486/0422 →
SECURITY INTEREST Recorded Jun 29, 2018
From: RPX CORPORATION
To: JEFFERIES FINANCE LLC
Reel/Frame 046486/0433 →
RELEASE (REEL 038041 / FRAME 0001) Recorded Jan 2, 2018
From: JPMORGAN CHASE BANK, N.A.
To: RPX CORPORATION; RPX CLEARINGHOUSE LLC
Reel/Frame 044970/0030 →
SECURITY AGREEMENT Recorded Mar 9, 2016
From: RPX CORPORATION; RPX CLEARINGHOUSE LLC
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038041/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2014
From: PANASONIC CORPORATION (FORMERLY KNOWN AS MATSUSHITA ELECTRIC INDUSTRIAL, CO., LTD.)
To: RPX CORPORATION
Reel/Frame 032826/0585 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2014
From: NAKAGAWA, HIDEO; TAMAOKA, EIJI; KUBOTA, MASAFUMI; UEDA, TETSUYA
To: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Reel/Frame 031934/0214 →
CHANGE OF NAME Recorded Jan 10, 2014
From: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
To: PANASONIC CORPORATION
Reel/Frame 031961/0079 →