NROM fabrication method
View Patent ↗A method of fabricating an oxide-nitride-oxide (ONO) layer in a memory cell to retain charge well in the nitride layer includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a top oxide layer, thereby causing oxygen to be introduced into the nitride layer. Another method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer and oxidizing a portion of a top oxide layer, thereby causing oxygen to be introduced into the nitride layer and depositing a remaining portion of the top oxide layer, thereby assisting in controlling the amount of oxygen introduced into the nitride layer. A further method includes the steps of forming a bottom oxide layer on a substrate, depositing a nitride layer, depositing a portion of a top oxide layer and oxidizing a remaining portion of the top oxide layer, thereby causing oxygen to be introduced into the nitride layer.
1. A programmable, read only memory device comprising:
two diffusion areas in a substrate and a channel formed therebetween;
an ONO layer at least over said channel comprising:
a first oxide layer;
a substantially oxygenated nitride layer having a thickness of 100 angstroms or less overlaying said first oxide layer; and
a second oxide layer overlaying said nitride layer,
said first and second oxide layers having a thickness that is the same order of magnitude as said nitride layer; and
a gate at least above said ONO layer.
2. A non-volatile memory cell comprising:
a charge trapping layer at least partially including silicon nitride, wherein said silicon nitride includes an annealed nitride portion and at least a portion of which is located substantially above a channel of the cell.
3. The non-volatile memory cell according to claim 2 wherein said silicon nitride has a thickness of between approximately 20-150 angstroms.
4. The non-volatile memory cell according to claim 2 wherein said silicon nitride has a thickness of between approximately 10-50 angstroms.
5. The non-volatile memory cell according to claim 2 wherein a non-volatile memory cell further including an oxide layer located substantially between at least a portion of the charge trapping layer and at least a portion of the channel.
6. The non-volatile memory cell according to claim 2 wherein said silicon nitride is adulterated with a non-native impurity selected from the group consisting of oxygen, boron, carbon and polycrystalline silicon.
7. The non-volatile memory cell accordig to claim 2 wherein said silicon nitride is enhanced with oxygen.