Hybrid circuit having nanotube electromechanical memory
View Patent ↗A hybrid memory system having electromechanical memory cells is disclosed. A memory cell core circuit has an array of electromechanical memory cells, in which each cell is a crossbar junction at least one element of which is a nanotube or a nanotube ribbon. An access circuit provides array addresses to the memory cell core circuit to select at least one corresponding cell. The access circuit is constructed of semiconductor circuit elements.
1. A hybrid memory circuit, comprising:
a substrate;
an electrically conductive trace disposed on the substrate;
a deflectable article having at least one nanotube disposed in spaced separation relative to the conductive trace, and wherein the position of the deflectable article represents a memory state of the memory circuit; and
an electronic selection circuit for selecting the deflectable article for operation in response to receiving a memory cell address.
2. A hybrid memory system, comprising:
an arrangement of memory cells, each memory cell having a nanotube element for storing memory states, wherein the nanotube element comprises a nanotube switch having a portion of nanotube fabric, the nanotube fabric comprising a plurality of nanotubes, and wherein the nanotube switch is capable of switching states in which different switch states correspond to different memory states;
a cell selector circuit for receiving memory address information and for selecting at least one corresponding cell in response thereto, the cell selector circuit being constructed of transistors.
3. The hybrid memory circuit of claim 1 , wherein the deflectable article is a nanotube ribbon.
4. The hybrid memory circuit of claim 1 , wherein the deflectable article comprises a nanotube fabric, the nanotube fabric having a plurality of unaligned nanotubes.
5. The hybrid memory circuit of claim 1 , wherein the electronic selection circuit receiving the memory cell address comprises receiving electrical stimulus applied to at least one address line.
6. The hybrid memory circuit of claim 1 , wherein the electronic selection circuit comprises at least one transistor.
7. The hybrid memory circuit of claim 1 , wherein the electronic selection circuit comprises at least one field programmable semiconductor device responsive to memory cell address information electrically transmitted on at least one address line.
8. The hybrid memory circuit of claim 1 , wherein the deflectable article is capable of nonvolatilely retaining the position representing a memory state of the memory circuit.
9. The hybrid memory circuit of claim 1 , the deflectable article having a first and a second position representing a first and a second memory state of the memory circuit, respectively, wherein in the first position the deflectable article is in electrical communication with the conductive trace and wherein in the second position the deflectable article is not in electrical communication with the conductive trace.