Method and apparatus for forming a semiconductor substrate with a layer structure of activated dopants
View Patent ↗Methods of forming semiconductor devices with a layered structure of thin and well defined layer of activated dopants, are disclosed. In a preferred method, a region in a semiconductor substrate is amorphized, after which the region is implanted with a first dopant at a first doping concentration. Then a solid phase epitaxy regrowth step is performed on a thin layer of desired thickness of the amorphized region, in order to activate the first dopant only in this thin layer. Subsequently, a second dopant is implanted in the remaining amorphous region at a second doping concentration. Subsequent annealing of the substrate activates the second dopant only in said remaining region, so a very abrupt transition between dopant characteristics of the thin layer with first dopant and the region with the second dopant is obtained.
1. A method of providing a layer structure of activated dopants in a semiconductor substrate, the method comprising:
forming at least one amorphous sub-volume in a semiconductor substrate;
implanting a first dopant in the amorphous sub-volume;
activating the first dopant only in a first region of the amorphous sub-volume to form a boundary region within the sub-volume, wherein activating comprises recrystallizing the first region;
implanting a second dopant in a second region of the amorphous sub-volume after activating the first dopant, and
activating the second dopant in the second region of the amorphous sub-volume.
2. The method of claim 1 , wherein forming the amorphous sub-volume comprises performing a pre-amorphization implant step.
3. The method of claim 1 , wherein activating the first dopant comprises performing a first SPER step.
4. The method of claim 3 , wherein activating the second dopant comprises performing a second SPER step.
5. The method of claim 1 , wherein activating the second dopant comprises performing a laser thermal anneal step.
6. The method of claim 4 , wherein performing the first SPER step and the second SPER step comprises applying a temperature of between about 500° C. and 800° C.
7. The method of claim 6 , wherein performing the first SPER step and the second SPER step comprises applying a temperature of between about 550° C. and 650° C.
8. The method of claim 4 , wherein performing the first SPER step and the second SPER step comprise using an activation period of less than about 1000 seconds.
9. The method of claim 8 , wherein the activation period is shorter than about 5 seconds.
10. The method of claim 1 , wherein implanting and activating the first dopant is used to form a pocket in the semiconductor substrate.
11. The method of claim 10 , wherein implanting and activating the second dopant is used to form an extension at least partially surrounded by the pocket.
12. The method of claim 1 , wherein forming the boundary region comprises forming a layer with a thickness of between about 0.5 and 5 nm.
13. The method of claim 12 , wherein the thickness of the boundary region is between about 1 and 3 nm.
14. The method of claim 1 , wherein implanting the first dopant comprises implanting the first dopant with a maximum concentration in the boundary region.
15. A method of forming a transistor comprising:
forming a first amorphous region and a second amorphous region in a semiconductor substrate;
implanting a first dopant in the amorphous regions;
activating the first dopant in portions of the amorphous regions to form a first boundary region lining the first amorphous region and a second boundary region lining the second amorphous region;
implanting a second dopant in the amorphous regions; and
activating the second dopant in each amorphous region to form a source extension at least partially surrounded by the first boundary region and a drain extension at least partially surrounded by the second boundary region.