Method for forming a notched gate insulator for advanced MIS semiconductor devices and devices thus obtained
View Patent ↗Methods of providing a semiconductor device with a control electrode structure having a controlled overlap between control electrode and first and second main electrode extensions without many spacers are disclosed. A preferred method provides a step of etching back an insulating layer performed after amorphizing and implanting the main electrode extensions. Preferably, the step that amorphizes the extensions also partly amorphizes the insulating layer. Because etch rates of amorphous insulator and crystalline insulator differ, the amorphized portion of the insulating layer may serve as a natural etch stop to enable even better fine-tuning of the overlap. Corresponding semiconductor devices are also provided.
1. A method of forming a semiconductor device structure comprising:
forming an insulating layer and a control electrode on a substrate;
amorphizing a first region of the substrate and a first region of the insulating layer, wherein amorphizing the first regions comprises accelerating ions under a first angle with respect to a direction substantially perpendicular to the substrate;
amorphizing a second region of the substrate and a second region of the insulating layer, wherein amorphizing the second regions comprises accelerating ions under a second angle with respect to the direction substantially perpendicular to the substrate;
implanting ions into the amorphized regions of the substrate to form a source extension and a drain extension, wherein implanting ions comprises implanting ions using a third angle with respect to the direction substantially perpendicular to the substrate;
etching back the two amorphized regions of the insulating layer to form recesses that reduce capacitive overlap between the control electrode and first and second main electrode extensions.
2. The method of claim 1 , further comprising activating dopants in the source and drain extensions.
3. The method of claim 2 , wherein activating dopants in the source and drain extensions comprises performing an annealing step selected from the group consisting of rapid thermal annealing, flash rapid thermal annealing, solid phase epitaxy regrowth and laser thermal annealing.
4. The method of claim 2 , wherein activating dopants in the source and drain extensions is performed after etching back the insulating layer.
5. The method of claim 1 , wherein the first angle and the second angle are substantially the same.
6. The method of claim 5 , wherein the first angle, the second angle, and the third angle are substantially the same.
7. The method of claim 1 , wherein the first angle, the second angle, and the third angle are between about 0° and 45° with respect to the direction substantially perpendicular to the substrate.
8. The method of claim 1 , wherein etching back the insulating layer comprises performing a wet etch with a hydrofluoric acid solution with a hydrofluoric acid concentration of between about 0.1% and 10%.
9. A method of controlling control electrode overlap in a semiconductor device, comprising
forming a main electrode in a substrate;
forming an insulating layer and a control electrode over the substrate;
amorphizing a connection region in the substrate between the main electrode and the control electrode and a sacrificial region in the insulating layer;
implanting dopants in the connection region after amorphizing the connecting layer;
activating the dopants in the connection region to form an electrode extension; and
removing the sacrificial region in the insulating layer after activating the dopants to form a recess between the electrode extension and the control electrode.
10. The method of claim 9 , wherein activating the dopants comprises performing an annealing step.
11. The method of claim 9 , wherein activating the dopants in the connection region comprises performing an annealing process.