Non-volatile memory system having a programmably selectable boot code section size
View Patent ↗A non-volatile memory system is presented having a boot code section, wherein the size of the boot code section may be programmably selected. One embodiment of the non-volatile memory system includes a memory array, a logic unit, a control unit, and a program store. The memory array includes multiple non-volatile memory cells (e.g., flash EEPROM cells). The memory array is divided into memory blocks of equal size. A number of the memory blocks are allocated for boot code storage, forming a boot code section of the memory array. The control unit controls storage of data within and retrieval of data from the memory array. The control unit includes a configuration register having a boot code section size field. The contents of the boot code section size field determine the number of memory blocks making up the boot code section. The logic unit is coupled between the control unit and the memory array, and receives address, data, and control signals from an external source. The logic unit provides the address, data, and control signals to the control unit and to the memory array. The program store stores instructions and data which determine the functionality of the control unit. Commands and configuration data are conveyed to the non-volatile memory system using predetermined sequences of bus write cycles. One embodiment of a computer system includes a central processing unit (CPU), and expansion bus, a memory bus, chip set logic, and the non-volatile memory system.
1. A non-volatile memory device, comprising:
a memory array comprising a plurality of memory blocks, wherein a boot code section of the memory array is configured to store boot code; and
a control unit configurable by software to vary the size of the boot code section;
wherein the control unit comprises a storage unit, wherein a portion of the storage unit is configured to store information indicating a size of the boot code section;
wherein the storage unit is configured so that, when the storage unit is erased, the information has a first value indicating that the size of the boot code section is a default size; and
wherein the storage unit is programmable so that the information has a second value, different from the first value, indicating that the size of the boot code section is the default size.
2. The non-volatile memory device of claim 1 ,
wherein the control unit is configurable by software to vary the size of the boot code section by modifying the information stored in the portion of the storage unit indicating the size of the boot code section.
3. The non-volatile memory device of claim 2 , wherein the storage unit comprises a plurality of non-volatile memory cells.
4. The non-volatile memory device of claim 2 , wherein the information indicates the size of the boot code section by indicating a number of the memory blocks comprised within the boot code section.
5. The non-volatile memory device of claim 2 , wherein the storage unit further comprises other configuration data for the non-volatile memory device.
6. The non-volatile memory device of claim 5 , wherein the control unit is further configured to receive new configuration data from an external source and to store the new configuration data in the storage unit.
7. The non-volatile memory device of claim 2 , wherein the storage unit is comprised within a register comprised within the control unit.
8. The non-volatile memory device of claim 2 , wherein the memory array and the control unit are formed upon a single monolithic semiconductor substrate.
9. The non-volatile memory device of claim 1 , wherein the boot code comprises a plurality of instructions used to initialize a central processing unit (CPU).
10. The non-volatile memory device of claim 1 , wherein the control unit is further configured to prevent erasure of the boot code section of the memory array.
11. The non-volatile memory device of claim 10 , wherein the control unit is further configured to allow the boot code stored within the boot code section to be modified.
12. The non-volatile memory device of claim 1 , further comprising a hardware mechanism configured to prevent erasure of the boot code section of the memory array.
13. The non-volatile memory device of claim 1 , wherein the control unit is further configured to modify the size of the boot code section in response to receiving a predetermined sequence of bus write cycles.
14. The non-volatile memory device of claim 1 , wherein each of the memory blocks comprises a plurality of non-volatile memory cells.
15. The non-volatile memory device of claim 14 , wherein the plurality of non-volatile memory cells comprises a plurality of flash EEPROM cells.
16. The non-volatile memory device of claim 1 , wherein the memory array is further configured so that all of the memory cells comprised within a particular memory block can be erased simultaneously.
17. The non-volatile memory device of claim 1 , further comprising a logic unit coupled between the control unit and the memory array and configured to receive a first plurality of signals from an external source and to provide a second plurality of signals to the control unit and the memory array.
18. The non-volatile memory device of claim 17 , wherein both the first signals and the second signals comprise address, data, and control signals.
19. The non-volatile memory device of claim 1 , wherein the default size is 0 bytes.
20. The non-volatile memory device of claim 1 , further comprising a program store configured to store instructions and data which determine the functionality of the control unit.
21. The non-volatile memory device of claim 1 , wherein the memory array is a flash memory array.
22. A computer system, comprising:
a central processing unit (CPU) configured to execute instructions;
a bus coupled to the CPU; and
a non-volatile memory unit coupled to the bus, wherein the non-volatile memory unit comprises:
a memory array comprising a plurality of non-volatile memory blocks, wherein a boot code section of the memory array is configured to store boot code used by the CPU; and
a control unit configurable by software to vary the size of the boot code section;
wherein the control unit comprises a configuration register including a boot section size field, wherein the boot section size field is configured to store information indicating a size of the boot code section;
wherein the configuration register is configured so that, when the configuration register is erased, the information has a first value indicating that the size of the boot code section is a default size; and
wherein the configuration register is programmable so that the information has a second value, different from the first value, indicating that the size of the boot code section is the default size.
23. The computer system of claim 22 , wherein the control unit is configured to modify the information stored in the boot section size field in response to signals on the bus.
24. The computer system of claim 23 , wherein the signals on the bus comprise a predetermined sequence of bus write cycles.
25. The computer system of claim 23 , wherein a portion of the signals on the bus indicate a new size of the boot code section, and wherein the control unit is further configured to modify the information to indicate the new size.
26. The computer system of claim 23 , wherein the information indicates the size of the boot code section by indicating a number of the non-volatile memory blocks comprised within the boot code section.
27. The computer system of claim 22 , wherein the control unit is further configured to prevent erasure of the boot code section.
28. The computer system of claim 22 , wherein the default size is 0 bytes.
29. The computer system of claim 22 , wherein the memory array and the control unit are formed upon a single monolithic semiconductor substrate.
30. The computer system of claim 22 , wherein the memory array is a flash memory array.
31. A memory device, comprising:
a memory array comprising a plurality of sections; and
a control unit configured to protect one of the sections from erasure while allowing erasure of one or more other ones of the sections, wherein the control unit is configurable by software to vary the size of the protected section;
wherein the control unit comprises a storage unit, wherein a portion of the storage unit is configured to store information indicating a size of a boot code section;
wherein the storage unit is configured so that, when the storage unit is erased, the information has a first value indicating that the size of the boot code section is a default size; and
wherein the storage unit is programmable so that the information has a second value, different from the first value, indicating that the size of the boot code section is the default size.
32. A computer system, comprising:
a processor;
a bus coupled to the processor; and
a memory unit coupled to the bus and accessible by the processor, wherein the memory unit comprises:
a memory array comprising a plurality of sections; and
a control unit configured to protect one of the sections from erasure while allowing erasure of one or more other ones of the sections, wherein the control unit is configurable by software to vary the size of the protected section;
wherein the control unit comprises a storage unit, wherein a portion of the storage unit is configured to store information indicating a size of a boot code section;
wherein the storage unit is configured so that, when the storage unit is erased, the information has a first value indicating that the size of the boot code section is a default size; and
wherein the storage unit is programmable so that the information has a second value, different from the first value, indicating that the size of the boot code section is the default size.