Trench buried bit line memory devices and methods thereof
View Patent ↗A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
1. A memory cell comprising:
a trench formed in a base substrate that is generally parallel to a continuous strip of active area;
a spacer within said trench lining at least a portion of the walls of said trench;
a conductive bit line deposited within said trench, wherein said conductive bit line is recessed below an uppermost surface of said base substrate and within said base substrate so that an uppermost surface of said conductive bit line is at a distance that is sufficiently deep to avoid gate induced drain leakage effects, wherein said distance is defined by a combined distance of a junction depth plus a depletion width of said transistor; and
a bit line strap coupled between said conductive bit line and said active area at least about said uppermost surface of said base substrate.
2. The memory cell of claim 1 , wherein said base substrate has a first base layer and a second base layer.
3. The memory cell of claim 2 , wherein said continuous strip of active area is formed on said first base layer of said base substrate.
4. The memory cell of claim 2 , wherein said conductive bit line is etched back below an uppermost surface of said second base layer of said base substrate.
5. The memory cell of claim 2 , wherein said spacer is formed by thermally growing a first layer of oxide and depositing a second layer of oxide over said first layer of oxide.
6. The memory cell of claim 5 , wherein said spacer is further formed by depositing a nitride layer over said second layer of oxide.
7. The memory cell of claim 1 , wherein said spacer is formed to have a thickness of about one fourth the minimum realizable feature size, wherein the minimum realizable feature size is about 1000 Angstroms.
8. The memory cell of claim 1 , further comprising:
an insulating capping layer formed within said trench over said conductive bit line.
9. The memory cell of claim 8 , wherein said insulating cap comprises a layer of nitride and a layer of insulating material over said nitride layer.
10. The memory cell of claim 8 , wherein said insulating cap further comprising:
a capping layer of nitride deposited over said conductive bit line; and
a capping insulating material of HDP deposited over said capping layer of nitride.
11. The memory cell of claim 1 , further comprising:
a transistor, including a first source/drain region and a second source/drain region, formed in said active area; and
a word line coupled to said transistor defining a transistor gate.
12. The memory cell of claim 11 , further comprising:
a capacitor formed over said base substrate that electrically couples said capacitor to said transistor.
13. The memory cell of claim 1 , wherein said bit line strap is isolated from said active area by an insulative spacer.
14. The memory cell of claim 1 , wherein said conductive bit line comprises a layer of titanium alloy containing tungsten.
15. A memory cell comprising:
a trench formed in a base substrate that is generally parallel to a continuous strip of active area;
a spacer within said trench lining at least a portion of the walls of said trench;
a conductive bit line deposited within said trench and etched back below an uppermost surface of said second base layer of said base substrate, wherein an uppermost surface of said conductive bit line is at a distance define by a combined distance of a junction depth plus a depletion width of a transistor; and
a bit line strap coupled between said conductive bit line and said active area at least about said uppermost surface of said base substrate.
16. A memory cell comprising:
a trench formed in a base substrate that is generally parallel to a continuous strip of active area;
a spacer lining a portion of the walls of said trench;
a conductive bit line deposited within said trench and recessed below an uppermost surface of said base substrate, wherein said conductive bit line is recessed within said base substrate such that an uppermost surface of said conductive bit line is at a distance that is sufficiently deep to avoid gate induced drain leakage effects, wherein said distance is defined by a combined distance of a junction depth plus a depletion width of said transistor;
a transistor, including a first source/drain region and a second source/drain region, formed in said active area; and
a bit line strap coupled between said conductive bit line and said active area at least about said uppermost surface of said base substrate and coupled between said first source/drain region through said portion of said walls of said trench.
17. A memory cell, comprising:
a trench formed in a base substrate that is generally parallel to a continuous strip of active area;
a transistor formed in a first type well in said base substrate comprising a channel between a first source/drain region and a second source/drain region;
a spacer lining a portion of the walls of said trench;
a conductive bit line deposited within said trench and recessed below an uppermost surface of said base substrate such that an uppermost surface of said conductive bit line is at a distance define by a combined distance of a junction depth plus a depletion width of said transistor; and
a bit line strap coupling said conductive bit line with said first source/drain region of said transistor.
18. A memory cell comprising:
a trench formed in a base substrate that is generally parallel to a continuous strip of active area and is etched to a depth greater than twice a minimum realizable feature size,
wherein the minimum realizable feature size is about 1000 Angstroms;
a spacer lining a portion of the walls of said trench;
a conductive bit line deposited within said trench and recessed below an uppermost surface of said base substrate such that an uppermost surface of said conductive bit line is at a distance define by a combined distance of a junction depth plus a depletion width of said transistor; and
a bit line strap coupled between said conductive bit line and said active area at least about said uppermost surface of said base substrate.
19. The memory cell of claim 18 , wherein said base substrate has a first base layer and a second base layer.
20. The memory cell of claim 19 , wherein said first base layer is doped with a first type of impurity and said second base layer comprises a buried layer doped with a second type impurity.
21. The memory cell of claim 19 , wherein said first base layer comprises a P-type semiconductor material and said second base layer comprises an N+ buried layer.
22. The memory cell of claim 19 , wherein said first base layer comprises a semiconductor layer and said second base layer comprises an insulator layer.
23. A memory cell comprising:
a P-type well formed within a base substrate;
an N-type active area formed within said P-type well;
a trench formed within said base substrate generally adjacent to said N-type active area;
a spacer lining at least a portion of the walls of said trench;
a conductive bit line deposited within said trench and recessed below an uppermost surface of said base substrate such that an uppermost surface of said conductive bit line is at a distance define by a combined distance of a junction depth plus a depletion width of said transistor; and
a line strap coupled between said conductive bit line and said N-type active area at least about said uppermost surface of said base substrate and coupled through said at least said portion of said walls of said trench.