Mechanism to guarantee forward progress for incoming coherent input/output (I/O) transactions for caching I/O agent on address conflict with processor transactions

1. A forward progress module, comprising:

an address conflict checking module to compare a first memory address from a first coherent input/output (I/O) transaction with a memory address corresponding to a processor-issued transaction to determine if an address conflict exists; and

a processor module to complete the processor-issued transaction that has the address conflict, reject the first coherent I/O transaction, hold remaining processor-issued transactions other than the processor-issued transaction that have the address conflict with the first memory address, and transmit the rejected first coherent I/O transaction to an external I/O device due to the address conflict.

2. The forward progress module of claim 1 , wherein the processor module waits for the rejected first coherent I/O transaction to return from the external I/O device, and completes the rejected first coherent I/O transaction once it returns.

3. The forward progress module of claim 2 , wherein the processor module releases the remaining processor transactions once the rejected first coherent I/O transaction has been completed and allows the remaining processor transactions to be completed by the processor module.

4. The forward progress module of claim 1 , wherein the forward progress module is located in a switching device.

5. The forward progress module of claim 1 , wherein the forward progress module is located in an input/output (I/O) device.

6. The forward progress module of claim 1 , further including a processor transaction buffer to store the at least one processor-issued transaction.

7. The forward progress module of claim 6 , wherein the processor transaction buffer stores a single processor-issued transaction of the remaining processor-issued transactions that request the first memory address.

8. The forward progress module of claim 6 , wherein the processor transaction buffer stores multiple processor-issued transactions of the remaining processor-issued transaction that request the first memory address.

9. The forward progress module of claim 1 , wherein the remaining processor-issued transactions are transmitted to a processor bus.

10. The forward progress module of claim 1 , further including a buffer module to store the first coherent I/O transaction.

11. A method to forward transactions, comprising:

comparing a first address from a first coherent input/output (I/O) transaction with an address from a processor-issued transaction to determine if an address conflict exists;

completing the processor-issued transaction if the address conflict exists and rejecting the first coherent I/O transaction;

holding remaining processor transactions that have the address conflict with the first address of the first coherent I/O transaction; and

transmitting the rejected first coherent I/O transaction, after the first coherent I/O transaction is rejected, to an external I/O device due to the address conflict.

12. The method of claim 11 , further including waiting for the rejected first coherent I/O transaction to return from the external I/O device, and completing the rejected first coherent I/O transaction.

13. The method of claim 12 , further including releasing the remaining processor transactions once the rejected first coherent I/O transaction has been completed and allowing the remaining processor transactions to be completed by a processor.

14. The method of claim 12 , wherein an I/O transaction buffer stores the first coherent I/O transaction, transmits the rejected first coherent I/O transaction to the external I/O device, waits for the rejected first coherent I/O transaction to return from the external I/O device, and transmits the rejected first coherent I/O transaction to a processor module to complete the rejected first coherent I/O transaction.

15. The method of claim 11 , wherein a single processor-issued transaction of the remaining processor transactions of the at least one processor transaction is held in a processor transaction buffer.

16. The method of claim 15 , wherein a plurality of the remaining processor transactions are transmitted to a processor bus.

17. A program code storage device, comprising:

a machine-readable storage medium; and

machine-readable program code, stored on the machine-readable storage medium, the machine readable program code having instructions, which when executed cause a computer, to:

compare a first address from a first coherent input/output (I/O) transaction with an address from a processor-issued transaction to determine if an address conflict exists;

complete the processor-issued transaction if the address conflict exists and reject the first coherent I/O transaction;

hold remaining processor transactions that have the address conflict with the first address of the first coherent I/O transaction; and

transmit the rejected first coherent I/O transaction to an external I/O device due to the address conflict.

18. The program code storage device of claim 17 , further including instructions, which when executed cause the computer to wait for the rejected first coherent I/O transaction return from the external I/O device and to complete the rejected first coherent I/O transaction.

19. The program code storage device of claim 18 , further including instructions, which when executed cause the computer to release the remaining processor transactions once the rejected first coherent I/O transaction has been completed and to complete, utilizing a processor, the remaining processor transactions.

20. The program code storage device of claim 17 , further including instructions, which when executed, cause the computer to hold a single processor-issued transaction of the remaining processor transactions in a processor transaction buffer and to transmit a plurality of the remaining processor transactions to a processor bus.