Anisotropic conductive film and bump, and packaging structure of semiconductor having the same
View Patent ↗In an anisotropic conductive film including conductive particles, and a bump, and a packaging structure of a semiconductor chip having the anisotropic conductive film and the bump, the anisotropic conductive film includes a resin layer and the conductive particles. The anisotropic conductive film electrically connects an electrode of a substrate and the bump of a semiconductor chip. A volume ratio of the conductive particles to the resin layer is about 0.1 to about 0.12. A number of the conductive particles per cubic millimeter (mm 3 ) is about 4 millions to about 7 millions. A standard deviation of heights of the bumps is no more than about 0.25. An interval between each of the bumps and an electrode of the substrate is no more than about 1.3 μm. Therefore, the size of each of the conductive particles is optimized so that a failure probability of the open circuit is decreased.
1. An anisotropic conductive film electrically connecting an electrode of a substrate and a bump of a semiconductor chip, the anisotropic conductive film comprising:
a resin layer; and
a plurality of conductive particles in the resin layer, a volume ratio of the conductive particles to the resin layer being about 0.1 to about 0.12, a diameter of each of the conductive particles being not less than 3.1 μm and not more than 4.2 μm, a number of the conductive particles per one cubic millimeter (mm 3 ) being about 4 millions to about 7 millions.
2. The anisotropic conductive film of claim 1 , wherein an area of the bump is about 1,000 μm 2 to about 2000 μm 2
3. The anisotropic conductive film of claim 1 , wherein an area of the bump is about 2,000 μm 2 to about 3,000 μm 2
4. Bumps formed on a semiconductor chip formed opposite a substrate, wherein the bumps have at least two different heights and are electrically connected to the substrate by an anisotropic conductive film, wherein a standard deviation of heights of the bumps is no more than about 0.25, and heights of the bumps are more than about 13.3 μm.
5. The bumps of claim 4 , wherein a diameter of each of the conductive particles is about 3.1 μm to about 4.2 μm, and an area of the bump is about 1,000 μm 2 to about 2,000 μm 2 .
6. A packaging structure of a semiconductor comprising:
a semiconductor chip including a bump having a height that is more than about 13.3 μm;
a substrate having an electrode;
an anisotropic conductive film including a plurality of conductive particles to electrically connect the bump and the electrode, a number of the conductive particles per one cubic millimeter (mm 3 ) being about 4 millions to about 7 millions,
wherein the bump is formed on the semiconductor chip opposite the substrate; and
a plurality of bumps having at least two different heights, wherein a standard deviation of heights of the bumps is no more than about 0.25.
7. The packaging structure of claim 6 , wherein a diameter of each of the conductive particles is about 3.1 μm to about 4.2 μm, and an area of the bump is about 1,000 μm 2 to about 2,000 μm 2 .
8. The packaging structure of claim 6 , wherein a diameter of each of the conductive particles is about 3.5 μm, and an area of the bump is about 1,000 μm 2 to about 2,000 μm 2 .
9. The packaging structure of claim 6 , wherein a diameter of each of the conductive particles is no more than about 4.8 μm, and an area of the bump is about 2,000 μm 2 to about 3,000 μm 2 .
10. The packaging structure of claim 6 , wherein the anisotropic conductive film comprises:
a resin layer; and
the conductive particles in the resin layer, a volume ratio of the conductive particles to the resin layer being about 0.1 to about 0.12, the number of the conductive particles per one cubic millimeter (mm 3 ) being about 4 millions to about 7 millions.
11. The packaging structure of claim 6 , wherein the diameter of each of the conductive particles is about 3 μm to about 4 μm.
12. The packaging structure of claim 6 , wherein the diameter of each of the conductive particles is about 3.1 μm to about 4.2 μm.
13. The packaging structure of claim 6 , wherein an interval between the bump of the semiconductor chip and the electrode of the substrate is limited to less than about 1.3 μm.
14. The anisotropic conductive film of claim 1 , wherein an interval between the bump of the semiconductor chip and the electrode of the substrate is limited to less than about 1.3 μm.
15. The bumps of claim 4 , wherein an interval between each of the bumps and the electrode of the substrate is limited to less than about 1.3 μm.