Semiconductor memory device of hierarchy word type and sub word driver circuit

1. A sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, comprising:

a first NMOS transistor and a first PMOS transistor which are connected in series; and

a second NMOS transistor which is connected with a node between said first PMOS transistor and said first NMOS transistor,

wherein a source of said first PMOS transistor is connected with a sub word line inverted signal obtained by inverting said sub word line signal, and a source of said first NMOS transistor is connected with a first negative voltage,

a single main word line signal is connected to a gate of said first PMOS transistor and a gate of said first NMOS transistor, and

said sub word line signal is connected with a gate of said second NMOS transistor;

wherein:

a source of said second NMOS transistor is connected with said first negative voltage;

said first PMOS transistor and said first NMOS transistor have a first threshold voltage and a second threshold voltage, respectively, and

said second NMOS transistor has a third threshold voltage which is higher than said second threshold voltage.

2. The sub word driver circuit according to claim 1 , wherein said first PMOS transistor is back-biased to a positive voltage corresponding to a high level of said main word line signal, and

said first NMOS transistor and said second NMOS transistor are back-biased to a second negative voltage equal to or lower than said first negative voltage.

3. The sub word driver circuit according to claim 1 , wherein said second threshold voltage of said second NMOS transistor is substantially equal to a threshold voltage of a transistor in a memory cell.

4. A sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, comprising:

a first NMOS transistor and a first PMOS transistor which are connected in series; and

a second NMOS transistor connected between a first negative voltage and a node between said first PMOS transistor and said first NMOS transistor,

wherein a source of said first PMOS transistor is connected with a sub word line inverted signal obtained by inverting said sub word line, and

a single main word line signal is connected to a gate of said first PMOS transistor and a gate of said first NMOS transistor and said sub word line signal is connected to a gate of said second NMOS transistor.

5. The sub word driver circuit according to claim 4 , wherein said source of said first NMOS transistor is connected with said first negative voltage.

6. The sub word driver circuit according to claim 4 , wherein said first PMOS transistor is back-biased to a positive voltage corresponding to a high level of said main word line signal, and

said first NMOS transistor and said second NMOS transistor are back-biased to a second negative voltage equal to or lower than said first negative voltage.

7. The sub word driver circuit according to claim 4 , wherein said first PMOS transistor and said first NMOS transistor have a first threshold voltage and a second threshold voltage, respectively, and

said second NMOS transistor has a third threshold voltage which is higher than said second threshold voltage.

8. The sub word driver circuit according to claim 7 , wherein said second threshold voltage of said second NMOS transistor is substantially equal to a threshold voltage of a transistor in a memory cell.

9. A semiconductor memory device comprising:

a decoder which decodes an address to activate one of main word line signals and one of sub word signals for a memory cell sub array;

a first inverter which comprises a first PMOS transistor and a first NMOS transistor and which are connected with a first positive voltage, and inverts said activated sub word signal to generate a sub word line inverted signal;

a second inverter which comprises a second PMOS transistor and a second NMOS transistor, is connected between said sub word line inverted signal and a first negative voltage, and inverts said activated main word line signal to output an active word line signal which is supplied to said memory cell sub array; and

a third NMOS transistor which is connected between the output of said second inverter and said first negative voltage and has a gate receiving said activated sub word line signal;

wherein a source of said second NMOS transistor is connected with said first negative voltage;

said second NMOS transistor has a first threshold voltage, and

said third NMOS transistor has a second threshold voltage which is larger than the threshold voltage of said first threshold voltage.

10. The semiconductor memory device according to claim 9 , wherein each of said first and second PMOS transistors is back-biased to said first positive voltage, and

each of said first to third NMOS transistors is back-biased to a second negative voltage equal to or lower than said first negative voltage.

11. The semiconductor memory device according to claim 9 , wherein a source of said first NMOS transistor is connected with a ground voltage.

12. The semiconductor memory device according to claim 11 , wherein said first and second NMOS transistors have a first threshold voltage, which is substantially the same as that of said first or second PMOS transistor.

13. The semiconductor memory device according to claim 9 , wherein said second NMOS transistor has a first threshold voltage, and

each of said first and third NMOS transistors has a second threshold voltage which is larger than said first threshold voltage.

14. The semiconductor memory device according to claim 9 , wherein said second threshold voltage of each of said first and third NMOS transistors is substantially equal to a threshold voltage of a transistor in a memory cell.

15. The semiconductor memory device according to claim 9 , wherein said activated main word line signal, said activated sub word signal and said active word line signal pass on a memory cell array containing said memory cell sub array.