Chip-size package structure and method of the same
View Patent ↗The method includes a step of picking and placing standard good dice on a base for obtaining an appropriate and wider distance between dice than the original distance of dice on a wafer. The method of the chip-size package comprises the steps of separating dice on a wafer and picking and placing the dice on a base and filling a first material layer on the base into a space among the dice on the base. A dielectric layer with first openings is patterned to expose a portion of a conductive line of the dice. A conductive material is filled into the first openings and on the dielectric layer. Subsequently, a second material layer is formed to have a second openings exposing the conductive material and then welding solder balls on the second openings.
1. A process of chip-size package, comprising the steps of:
separating dice having pads on a wafer;
forming a first contact conductive layer on said dice to cover said pads;
forming a first dielectric layer on said first contact conductive layer and said dice to form first openings exposing said first contact conductive layer;
placing said dice including said pads, said first contact conductive layer and said first dielectric layer formed on a base;
filling a first material layer on said base into a space among said dice on said base;
patterning a second dielectric layer to form second openings exposing said first contact conductive layer;
filling and patterning a second conductive material layer into said second openings and on said second dielectric layer;
patterning a second material layer to form third openings exposing said conductive second material; and
welding solder balls on said third openings.
2. The process in claim 1 , further comprising a step of cleaning the surface of said wafer by RIE method before the step of separating said dice.
3. The process in claim 1 , wherein said first contact conductive layer is formed by CVD, PVD, sputter or electroplating.
4. The process in claim 1 , wherein said first contact conductive layer comprises Al.
5. The process in claim 1 , wherein said first contact conductive layer comprises Ti, Cu, and the combination thereof.
6. The process in claim 1 , wherein a thickness of said first contact conductive layer is 1˜2 μm.
7. The process in claim 1 , wherein said second conductive material layer comprises Cu, Ni, Au.
8. The process in claim 7 , wherein a thickness of said second conductive material layer is about 12˜18 μm.
9. The process in claim 1 , further comprising a second dielectric layer on said first contact conductive layer, said second dielectric layer comprising BCB, SINR, or silicon rubber.
10. The process in claim 9 , wherein a thickness of said second dielectric layer is about 1˜8 μm.
11. The process in claim 1 , wherein materials of said first material layer and said second material layer comprise UV curing type material or heat curing type material.
12. The process in claim 11 , wherein said first material layer comprises silicon rubber, epoxy, resin, STNR or BCB.
13. The process in claim 12 , wherein said first material layer is formed by a vacuum printing method and/or a photolithography method.
14. The process in claim 1 , further comprising a step of back lapping said wafer before the step of separating.
15. The process in claim 14 , wherein said wafer is back lapped to achieve a thickness about 50-300 μm.
16. The process in claim 1 , wherein said base comprises metal, alloy 42 or glass.
17. The process in claim 16 , wherein said metal comprises Fe, Co, Ni, and the combination thereof, and thickness of said base is about 200-300 μm.
18. The process in claim 17 , wherein a thickness of said glass is about 200-400 μm.
19. The process in claim 1 , wherein said dielectric layer is BCB, SINK, PI, silicon rubber.
20. The process in claim 19 , wherein thickness of said dielectric layer is about 2˜8 μm.
21. The process in claim 19 , wherein said dielectric layer is formed by a printing or spin coating method.
22. The process in claim 1 , wherein said first openings is formed by a laser trimming method or a photolithography method.
23. The process in claim 22 , further comprising a step of cleaning surface of said conductive lines of said die after the step of forming said first openings.
24. The process in claim 23 , farther comprising a step of performing a Chemical plating Cu or sputtering Ti/Cu or Al after the step of said cleaning surface of said conductive lines.
25. The process in claim 1 , wherein said second material layer comprises SINR, BCB or Solder Mask (Epoxy).
26. The process in claim 25 , wherein a thickness of said second material layer is about 20˜25 μm.
27. The process in claim 25 , wherein said second material layer is formed by a printing or coating method.
28. The process in claim 1 , farther comprising a step of cleaning surface of said conductive material after the step of forming said conductive material.
29. The process in claim 1 , further comprising a step of cutting said base to several chip-size dice pieces for FT (Final Testing) and BI(Bum In) after the step of said welding said solder balls in said second openings.
30. The process in claim 29 , further comprising a step of laser marking after the step of said FT (Final Testing).
31. The process in claim 1 , further comprising the steps after the step of said cutting said base to form single chip-size packages:
cutting said dice into a chip-size package; and
picking-and-placing said chip-size package into a tray for SMT (Surface Mounting Technique) process.
32. The process in claim 1 , wherein the step of welding said solder balls comprises:
placing said solder balls in said second openings by a stencil printing method; and
joining said solder balls with surfaces of said conductive material by an IR re-flow.