Accurate quiescent current control scheme in floating controlled class AB amplifier

1. An amplifier, comprising:

a driving stage including first pmos and nmos transistors coupled together;

an output stage connected to the driving stage and including second pmos and nmos transistors coupled together; and

a quiescent current control stage connected to the driving stage and including third pmos and nmos transistors coupled together and a fourth pmos and nmos transistors coupled together;

wherein a topology of the coupled third pmos and nmos transistors substantially matches a topology of the coupled first pmos and nmos transistors; and

wherein gates of the second pmos and nmos transistors are respectively coupled to sources of the first pmos and nmos transistors; and

wherein (i) a source of the third pmos is connected to a drain of the third nmos, (ii) a drain of the fourth pmos is connected to a gate of the third pmos, (iii) a gate of the fourth pmos is connected to a source of the third pmos and to a drain of the third nmos, (iv) a drain of the fourth nmos is directly connected to a gate of the first nmos, and (v) a gate of the fourth nmos is connected to a source of the third nmos.

2. The amplifier of claim 1 , wherein a source of the first pmos is connected to a drain of the first nmos and a source of the first nmos is connected to a drain of the first pmos.

3. An amplifier, comprising:

a driving stage including first pmos and nmos transistors, a source and a drain of the first pmos being respectively connected to a drain and a source of the first nmos; and

a current control stage connected to the driving stage and having at least a first portion including second pmos and nmos transistors;

wherein a source of the second pmos is coupled to a drain of the second nmos, gates of the second pmos and the first pmos are coupled together, and gates of the second nmos and the first nmos are coupled together; and

wherein a drain of the second pmos is directly connected to a first common node, a source of the second nmos is coupled to a first side of a current source, and a second side of the current source is coupled to the first common node.

4. The amplifier of claim 3 , further comprising:

a second portion including third pmos and nmos transistors, a gate of the third pmos being coupled the source of second pmos, and a gate of the third nmos being coupled to the source of the second nmos;

wherein a source of the third pmos is coupled to a second common node and a drain of the third nmos being coupled, at least indirectly, to the second common node; and

an output stage including fourth pmos and nmos transistors, the fourth pmos and nmos transistors having drains thereof coupled together, a gate of the fourth pmos is coupled to the source of the first pmos, and a gate of the fourth nmos is coupled to a source of the first nmos.

5. The amplifier of claim 4 , further comprising:

a first operational amplifier coupled to the third pmos; and

a second operational amplifier coupled to the third nmos.

6. The amplifier of claim 4 , further comprising:

a first amplifier having a first input port coupled to a common-mode voltage source, a second input port coupled to a drain of the third pmos, and an output port coupled to the gate of second pmos; and

a second amplifier having a first input port coupled to the common-mode voltage source, a second input port coupled to the drain of the third nmos, and an output port coupled to the gate of the second nmos.

7. The amplifier of claim 4 , further comprising an operational amplifier coupled to at least one of the third pmos and the third nmos transistors.